<AVRPART><MODULE_LIST>[ADMIN:CORE:PROGVOLT:POWER:LOCKBIT:MEMORY:INTERRUPT_VECTOR:PACKAGE:PROGRAMMING:FUSE:IO_MODULE:ICE_SETTINGS]</MODULE_LIST><ADMIN>
<PART_NAME>AT90PWM2</PART_NAME>
<SPEED>8MHz</SPEED>
<BUILD>139</BUILD>
<RELEASE_STATUS>RELEASED</RELEASE_STATUS>
<SIGNATURE>
<ADDR000>$1E</ADDR000>
<ADDR001>$93</ADDR001>
<ADDR002>$81</ADDR002>
</SIGNATURE>
</ADMIN>
<CORE>
<CORE_VERSION>V2E</CORE_VERSION>
<ID>AVRSimCoreV2.SimCoreV2</ID>
<NEW_INSTRUCTIONS>[]</NEW_INSTRUCTIONS>
<INSTRUCTIONS_NOT_SUPPORTED>[]</INSTRUCTIONS_NOT_SUPPORTED>
<RAMP_REGISTERS>[]</RAMP_REGISTERS>
<GP_REG_FILE>
<NMB_REG>32</NMB_REG>
<START_ADDR>$00</START_ADDR>
<X_REG_HIGH>$1B</X_REG_HIGH>
<X_REG_LOW>$1A</X_REG_LOW>
<Y_REG_HIGH>$1D</Y_REG_HIGH>
<Y_REG_LOW>$1C</Y_REG_LOW>
<Z_REG_HIGH>$1F</Z_REG_HIGH>
<Z_REG_LOW>$1E</Z_REG_LOW>
</GP_REG_FILE>
</CORE>
<PROGVOLT>
<SER_PROG_MIN_V>2.7</SER_PROG_MIN_V>
<SER_PROG_MAX_V>6.0</SER_PROG_MAX_V>
<PAR_PROG_MIN_V>4.5</PAR_PROG_MIN_V>
<PAR_PROG_MAX_V>5.5</PAR_PROG_MAX_V>
</PROGVOLT>
<POWER>
<CLOCK>4MHz</CLOCK>
<TEMP>25C</TEMP>
<ACTIVE>TBD mA</ACTIVE>
<IDLE>TBD mA</IDLE>
<POWER_DOWN>TBD uA</POWER_DOWN>
</POWER>
<LOCKBIT>
<ICON/>
<ID/>
<TEXT>[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled</TEXT>
<NMB_LOCK_BITS>6</NMB_LOCK_BITS>
<NMB_TEXT>11</NMB_TEXT>
<TEXT1>
<MASK>0x03</MASK>
<VALUE>0x03</VALUE>
<TEXT>Mode 1: No memory lock features enabled</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x03</MASK>
<VALUE>0x02</VALUE>
<TEXT>Mode 2: Further programming disabled</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x03</MASK>
<VALUE>0x00</VALUE>
<TEXT>Mode 3: Further programming and verification disabled</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x0C</MASK>
<VALUE>0x0C</VALUE>
<TEXT>Application Protection Mode 1: No lock on SPM and LPM in Application Section</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x0C</MASK>
<VALUE>0x08</VALUE>
<TEXT>Application Protection Mode 2: SPM prohibited in Application Section</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x0C</MASK>
<VALUE>0x00</VALUE>
<TEXT>Application Protection Mode 3: LPM and SPM prohibited in Application Section</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x0C</MASK>
<VALUE>0x04</VALUE>
<TEXT>Application Protection Mode 4: LPM prohibited in Application Section</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x30</MASK>
<VALUE>0x30</VALUE>
<TEXT>Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section</TEXT>
</TEXT8>
<TEXT9>
<MASK>0x30</MASK>
<VALUE>0x20</VALUE>
<TEXT>Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section</TEXT>
</TEXT9>
<TEXT10>
<MASK>0x30</MASK>
<VALUE>0x00</VALUE>
<TEXT>Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section</TEXT>
</TEXT10>
<TEXT11>
<MASK>0x30</MASK>
<VALUE>0x10</VALUE>
<TEXT>Boot Loader Protection Mode 4: LPM prohibited in Boot Loader Section</TEXT>
</TEXT11>
<LOCKBIT0>
<NAME>LB1</NAME>
<TEXT>Lock bit</TEXT>
</LOCKBIT0>
<LOCKBIT1>
<NAME>LB2</NAME>
<TEXT>Lock bit</TEXT>
</LOCKBIT1>
<LOCKBIT2>
<NAME>BLB01</NAME>
<TEXT>Boot Lock bit</TEXT>
</LOCKBIT2>
<LOCKBIT3>
<NAME>BLB02</NAME>
<TEXT>Boot Lock bit</TEXT>
</LOCKBIT3>
<LOCKBIT4>
<NAME>BLB11</NAME>
<TEXT>Boot lock bit</TEXT>
</LOCKBIT4>
<LOCKBIT5>
<NAME>BLB12</NAME>
<TEXT>Boot lock bit</TEXT>
</LOCKBIT5>
</LOCKBIT>
<MEMORY>
<ID>AVRSimMemory8bit.SimMemory8bit</ID>
<PROG_FLASH>8192</PROG_FLASH>
<EEPROM>512</EEPROM>
<INT_SRAM>
<SIZE>512</SIZE>
<START_ADDR>$0100</START_ADDR>
</INT_SRAM>
<EXT_SRAM>
<SIZE>0</SIZE>
<START_ADDR>NA</START_ADDR>
</EXT_SRAM>
<IO_MEMORY>
<IO_START_ADDR>$0000</IO_START_ADDR>
<IO_STOP_ADDR>$003F</IO_STOP_ADDR>
<EXT_IO_START_ADDR>$0060</EXT_IO_START_ADDR>
<EXT_IO_STOP_ADDR>$00FF</EXT_IO_STOP_ADDR>
<MEM_START_ADDR>$0020</MEM_START_ADDR>
<MEM_STOP_ADDR>$00FF</MEM_STOP_ADDR>
<PICR2H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xFF</MEM_ADDR>
<PICR2_8_MASK>0x01</PICR2_8_MASK><PICR2_9_MASK>0x02</PICR2_9_MASK><PICR2_10_MASK>0x04</PICR2_10_MASK><PICR2_11_MASK>0x08</PICR2_11_MASK></PICR2H>
<PICR2L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xFE</MEM_ADDR>
<PICR2_0_MASK>0x01</PICR2_0_MASK><PICR2_1_MASK>0x02</PICR2_1_MASK><PICR2_2_MASK>0x04</PICR2_2_MASK><PICR2_3_MASK>0x08</PICR2_3_MASK><PICR2_4_MASK>0x10</PICR2_4_MASK><PICR2_5_MASK>0x20</PICR2_5_MASK><PICR2_6_MASK>0x40</PICR2_6_MASK><PICR2_7_MASK>0x80</PICR2_7_MASK></PICR2L>
<PFRC2B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xFD</MEM_ADDR>
<PRFM2B0_MASK>0x01</PRFM2B0_MASK><PRFM2B1_MASK>0x02</PRFM2B1_MASK><PRFM2B2_MASK>0x04</PRFM2B2_MASK><PRFM2B3_MASK>0x08</PRFM2B3_MASK><PFLTE2B_MASK>0x10</PFLTE2B_MASK><PELEV2B_MASK>0x20</PELEV2B_MASK><PISEL2B_MASK>0x40</PISEL2B_MASK><PCAE2B_MASK>0x80</PCAE2B_MASK></PFRC2B>
<PFRC2A>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xFC</MEM_ADDR>
<PRFM2A0_MASK>0x01</PRFM2A0_MASK><PRFM2A1_MASK>0x02</PRFM2A1_MASK><PRFM2A2_MASK>0x04</PRFM2A2_MASK><PRFM2A3_MASK>0x08</PRFM2A3_MASK><PFLTE2A_MASK>0x10</PFLTE2A_MASK><PELEV2A_MASK>0x20</PELEV2A_MASK><PISEL2A_MASK>0x40</PISEL2A_MASK><PCAE2A_MASK>0x80</PCAE2A_MASK></PFRC2A>
<PCTL2>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xFB</MEM_ADDR>
<PRUN2_MASK>0x01</PRUN2_MASK><PCCYC2_MASK>0x02</PCCYC2_MASK><PARUN2_MASK>0x04</PARUN2_MASK><PAOC2A_MASK>0x08</PAOC2A_MASK><PAOC2B_MASK>0x10</PAOC2B_MASK><PBFM2_MASK>0x20</PBFM2_MASK><PPRE20_MASK>0x40</PPRE20_MASK><PPRE21_MASK>0x80</PPRE21_MASK></PCTL2>
<PCNF2>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xFA</MEM_ADDR>
<POME2_MASK>0x01</POME2_MASK><PCLKSEL2_MASK>0x02</PCLKSEL2_MASK><POP2_MASK>0x04</POP2_MASK><PMODE20_MASK>0x08</PMODE20_MASK><PMODE21_MASK>0x10</PMODE21_MASK><PLOCK2_MASK>0x20</PLOCK2_MASK><PALOCK2_MASK>0x40</PALOCK2_MASK><PFIFTY2_MASK>0x80</PFIFTY2_MASK></PCNF2>
<OCR2RBH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF9</MEM_ADDR>
<OCR2RB_8_MASK>0x01</OCR2RB_8_MASK><OCR2RB_9_MASK>0x02</OCR2RB_9_MASK><OCR2RB_10_MASK>0x04</OCR2RB_10_MASK><OCR2RB_11_MASK>0x08</OCR2RB_11_MASK><OCR2RB_12_MASK>0x10</OCR2RB_12_MASK><OCR2RB_13_MASK>0x20</OCR2RB_13_MASK><OCR2RB_14_MASK>0x40</OCR2RB_14_MASK><OCR2RB_15_MASK>0x80</OCR2RB_15_MASK></OCR2RBH>
<OCR2RBL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF8</MEM_ADDR>
<OCR2RB_0_MASK>0x01</OCR2RB_0_MASK><OCR2RB_1_MASK>0x02</OCR2RB_1_MASK><OCR2RB_2_MASK>0x04</OCR2RB_2_MASK><OCR2RB_3_MASK>0x08</OCR2RB_3_MASK><OCR2RB_4_MASK>0x10</OCR2RB_4_MASK><OCR2RB_5_MASK>0x20</OCR2RB_5_MASK><OCR2RB_6_MASK>0x40</OCR2RB_6_MASK><OCR2RB_7_MASK>0x80</OCR2RB_7_MASK></OCR2RBL>
<OCR2SBH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF7</MEM_ADDR>
<OCR2SB_8_MASK>0x01</OCR2SB_8_MASK><OCR2SB_9_MASK>0x02</OCR2SB_9_MASK><OCR2SB_10_MASK>0x04</OCR2SB_10_MASK><OCR2SB_11_MASK>0x08</OCR2SB_11_MASK></OCR2SBH>
<OCR2SBL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF6</MEM_ADDR>
<OCR2SB_0_MASK>0x01</OCR2SB_0_MASK><OCR2SB_1_MASK>0x02</OCR2SB_1_MASK><OCR2SB_2_MASK>0x04</OCR2SB_2_MASK><OCR2SB_3_MASK>0x08</OCR2SB_3_MASK><OCR2SB_4_MASK>0x10</OCR2SB_4_MASK><OCR2SB_5_MASK>0x20</OCR2SB_5_MASK><OCR2SB_6_MASK>0x40</OCR2SB_6_MASK><OCR2SB_7_MASK>0x80</OCR2SB_7_MASK></OCR2SBL>
<OCR2RAH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF5</MEM_ADDR>
<OCR2RA_8_MASK>0x01</OCR2RA_8_MASK><OCR2RA_9_MASK>0x02</OCR2RA_9_MASK><OCR2RA_10_MASK>0x04</OCR2RA_10_MASK><OCR2RA_11_MASK>0x08</OCR2RA_11_MASK></OCR2RAH>
<OCR2RAL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF4</MEM_ADDR>
<OCR2RA_0_MASK>0x01</OCR2RA_0_MASK><OCR2RA_1_MASK>0x02</OCR2RA_1_MASK><OCR2RA_2_MASK>0x04</OCR2RA_2_MASK><OCR2RA_3_MASK>0x08</OCR2RA_3_MASK><OCR2RA_4_MASK>0x10</OCR2RA_4_MASK><OCR2RA_5_MASK>0x20</OCR2RA_5_MASK><OCR2RA_6_MASK>0x40</OCR2RA_6_MASK><OCR2RA_7_MASK>0x80</OCR2RA_7_MASK></OCR2RAL>
<OCR2SAH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF3</MEM_ADDR>
<OCR2SA_8_MASK>0x01</OCR2SA_8_MASK><OCR2SA_9_MASK>0x02</OCR2SA_9_MASK><OCR2SA_10_MASK>0x04</OCR2SA_10_MASK><OCR2SA_11_MASK>0x08</OCR2SA_11_MASK></OCR2SAH>
<OCR2SAL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF2</MEM_ADDR>
<OCR2SA_0_MASK>0x01</OCR2SA_0_MASK><OCR2SA_1_MASK>0x02</OCR2SA_1_MASK><OCR2SA_2_MASK>0x04</OCR2SA_2_MASK><OCR2SA_3_MASK>0x08</OCR2SA_3_MASK><OCR2SA_4_MASK>0x10</OCR2SA_4_MASK><OCR2SA_5_MASK>0x20</OCR2SA_5_MASK><OCR2SA_6_MASK>0x40</OCR2SA_6_MASK><OCR2SA_7_MASK>0x80</OCR2SA_7_MASK></OCR2SAL>
<POM2>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF1</MEM_ADDR>
<POMV2A0_MASK>0x01</POMV2A0_MASK><POMV2A1_MASK>0x02</POMV2A1_MASK><POMV2A2_MASK>0x04</POMV2A2_MASK><POMV2A3_MASK>0x08</POMV2A3_MASK><POMV2B0_MASK>0x10</POMV2B0_MASK><POMV2B1_MASK>0x20</POMV2B1_MASK><POMV2B2_MASK>0x40</POMV2B2_MASK><POMV2B3_MASK>0x80</POMV2B3_MASK></POM2>
<PSOC2>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF0</MEM_ADDR>
<POEN2A_MASK>0x01</POEN2A_MASK><POEN2C_MASK>0x02</POEN2C_MASK><POEN2B_MASK>0x04</POEN2B_MASK><POEN2D_MASK>0x08</POEN2D_MASK><PSYNC2_0_MASK>0x10</PSYNC2_0_MASK><PSYNC2_1_MASK>0x20</PSYNC2_1_MASK><POS22_MASK>0x40</POS22_MASK><POS23_MASK>0x80</POS23_MASK></PSOC2>
<PICR1H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xEF</MEM_ADDR>
</PICR1H>
<PICR1L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xEE</MEM_ADDR>
</PICR1L>
<PFRC1B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xED</MEM_ADDR>
</PFRC1B>
<PFRC1A>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xEC</MEM_ADDR>
</PFRC1A>
<PCTL1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xEB</MEM_ADDR>
</PCTL1>
<PCNF1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xEA</MEM_ADDR>
</PCNF1>
<OCR1RBH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE9</MEM_ADDR>
</OCR1RBH>
<OCR1RBL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE8</MEM_ADDR>
</OCR1RBL>
<OCR1SBH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE7</MEM_ADDR>
</OCR1SBH>
<OCR1SBL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE6</MEM_ADDR>
</OCR1SBL>
<OCR1RAH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE5</MEM_ADDR>
</OCR1RAH>
<OCR1RAL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE4</MEM_ADDR>
</OCR1RAL>
<OCR1SAH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE3</MEM_ADDR>
</OCR1SAH>
<OCR1SAL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE2</MEM_ADDR>
</OCR1SAL>
<PSOC1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE0</MEM_ADDR>
</PSOC1>
<PICR0H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xDF</MEM_ADDR>
<PICR0_8_MASK>0x01</PICR0_8_MASK><PICR0_9_MASK>0x02</PICR0_9_MASK><PICR0_10_MASK>0x04</PICR0_10_MASK><PICR0_11_MASK>0x08</PICR0_11_MASK></PICR0H>
<PICR0L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xDE</MEM_ADDR>
<PICR0_0_MASK>0x01</PICR0_0_MASK><PICR0_1_MASK>0x02</PICR0_1_MASK><PICR0_2_MASK>0x04</PICR0_2_MASK><PICR0_3_MASK>0x08</PICR0_3_MASK><PICR0_4_MASK>0x10</PICR0_4_MASK><PICR0_5_MASK>0x20</PICR0_5_MASK><PICR0_6_MASK>0x40</PICR0_6_MASK><PICR0_7_MASK>0x80</PICR0_7_MASK></PICR0L>
<PFRC0B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xDD</MEM_ADDR>
<PRFM0B0_MASK>0x01</PRFM0B0_MASK><PRFM0B1_MASK>0x02</PRFM0B1_MASK><PRFM0B2_MASK>0x04</PRFM0B2_MASK><PRFM0B3_MASK>0x08</PRFM0B3_MASK><PFLTE0B_MASK>0x10</PFLTE0B_MASK><PELEV0B_MASK>0x20</PELEV0B_MASK><PISEL0B_MASK>0x40</PISEL0B_MASK><PCAE0B_MASK>0x80</PCAE0B_MASK></PFRC0B>
<PFRC0A>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xDC</MEM_ADDR>
<PRFM0A0_MASK>0x01</PRFM0A0_MASK><PRFM0A1_MASK>0x02</PRFM0A1_MASK><PRFM0A2_MASK>0x04</PRFM0A2_MASK><PRFM0A3_MASK>0x08</PRFM0A3_MASK><PFLTE0A_MASK>0x10</PFLTE0A_MASK><PELEV0A_MASK>0x20</PELEV0A_MASK><PISEL0A_MASK>0x40</PISEL0A_MASK><PCAE0A_MASK>0x80</PCAE0A_MASK></PFRC0A>
<PCTL0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xDB</MEM_ADDR>
<PRUN0_MASK>0x01</PRUN0_MASK><PCCYC0_MASK>0x02</PCCYC0_MASK><PARUN0_MASK>0x04</PARUN0_MASK><PAOC0A_MASK>0x08</PAOC0A_MASK><PAOC0B_MASK>0x10</PAOC0B_MASK><PBFM0_MASK>0x20</PBFM0_MASK><PPRE00_MASK>0x40</PPRE00_MASK><PPRE01_MASK>0x80</PPRE01_MASK></PCTL0>
<PCNF0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xDA</MEM_ADDR>
<PCLKSEL0_MASK>0x02</PCLKSEL0_MASK><POP0_MASK>0x04</POP0_MASK><PMODE00_MASK>0x08</PMODE00_MASK><PMODE01_MASK>0x10</PMODE01_MASK><PLOCK0_MASK>0x20</PLOCK0_MASK><PALOCK0_MASK>0x40</PALOCK0_MASK><PFIFTY0_MASK>0x80</PFIFTY0_MASK></PCNF0>
<OCR0RBH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD9</MEM_ADDR>
<OCR0RB_8_MASK>0x01</OCR0RB_8_MASK><OCR0RB_9_MASK>0x02</OCR0RB_9_MASK><OCR0RB_00_MASK>0x04</OCR0RB_00_MASK><OCR0RB_01_MASK>0x08</OCR0RB_01_MASK><OCR0RB_02_MASK>0x10</OCR0RB_02_MASK><OCR0RB_03_MASK>0x20</OCR0RB_03_MASK><OCR0RB_04_MASK>0x40</OCR0RB_04_MASK><OCR0RB_05_MASK>0x80</OCR0RB_05_MASK></OCR0RBH>
<OCR0RBL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD8</MEM_ADDR>
<OCR0RB_0_MASK>0x01</OCR0RB_0_MASK><OCR0RB_1_MASK>0x02</OCR0RB_1_MASK><OCR0RB_2_MASK>0x04</OCR0RB_2_MASK><OCR0RB_3_MASK>0x08</OCR0RB_3_MASK><OCR0RB_4_MASK>0x10</OCR0RB_4_MASK><OCR0RB_5_MASK>0x20</OCR0RB_5_MASK><OCR0RB_6_MASK>0x40</OCR0RB_6_MASK><OCR0RB_7_MASK>0x80</OCR0RB_7_MASK></OCR0RBL>
<OCR0SBH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD7</MEM_ADDR>
<OCR0SB_8_MASK>0x01</OCR0SB_8_MASK><OCR0SB_9_MASK>0x02</OCR0SB_9_MASK><OCR0SB_00_MASK>0x04</OCR0SB_00_MASK><OCR0SB_01_MASK>0x08</OCR0SB_01_MASK></OCR0SBH>
<OCR0SBL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD6</MEM_ADDR>
<OCR0SB_0_MASK>0x01</OCR0SB_0_MASK><OCR0SB_1_MASK>0x02</OCR0SB_1_MASK><OCR0SB_2_MASK>0x04</OCR0SB_2_MASK><OCR0SB_3_MASK>0x08</OCR0SB_3_MASK><OCR0SB_4_MASK>0x10</OCR0SB_4_MASK><OCR0SB_5_MASK>0x20</OCR0SB_5_MASK><OCR0SB_6_MASK>0x40</OCR0SB_6_MASK><OCR0SB_7_MASK>0x80</OCR0SB_7_MASK></OCR0SBL>
<OCR0RAH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD5</MEM_ADDR>
<OCR0RA_8_MASK>0x01</OCR0RA_8_MASK><OCR0RA_9_MASK>0x02</OCR0RA_9_MASK><OCR0RA_00_MASK>0x04</OCR0RA_00_MASK><OCR0RA_01_MASK>0x08</OCR0RA_01_MASK></OCR0RAH>
<OCR0RAL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD4</MEM_ADDR>
<OCR0RA_0_MASK>0x01</OCR0RA_0_MASK><OCR0RA_1_MASK>0x02</OCR0RA_1_MASK><OCR0RA_2_MASK>0x04</OCR0RA_2_MASK><OCR0RA_3_MASK>0x08</OCR0RA_3_MASK><OCR0RA_4_MASK>0x10</OCR0RA_4_MASK><OCR0RA_5_MASK>0x20</OCR0RA_5_MASK><OCR0RA_6_MASK>0x40</OCR0RA_6_MASK><OCR0RA_7_MASK>0x80</OCR0RA_7_MASK></OCR0RAL>
<OCR0SAH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD3</MEM_ADDR>
<OCR0SA_8_MASK>0x01</OCR0SA_8_MASK><OCR0SA_9_MASK>0x02</OCR0SA_9_MASK><OCR0SA_00_MASK>0x04</OCR0SA_00_MASK><OCR0SA_01_MASK>0x08</OCR0SA_01_MASK></OCR0SAH>
<OCR0SAL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD2</MEM_ADDR>
<OCR0SA_0_MASK>0x01</OCR0SA_0_MASK><OCR0SA_1_MASK>0x02</OCR0SA_1_MASK><OCR0SA_2_MASK>0x04</OCR0SA_2_MASK><OCR0SA_3_MASK>0x08</OCR0SA_3_MASK><OCR0SA_4_MASK>0x10</OCR0SA_4_MASK><OCR0SA_5_MASK>0x20</OCR0SA_5_MASK><OCR0SA_6_MASK>0x40</OCR0SA_6_MASK><OCR0SA_7_MASK>0x80</OCR0SA_7_MASK></OCR0SAL>
<PSOC0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD0</MEM_ADDR>
<POEN0A_MASK>0x01</POEN0A_MASK><POEN0B_MASK>0x04</POEN0B_MASK><PSYNC00_MASK>0x10</PSYNC00_MASK><PSYNC01_MASK>0x20</PSYNC01_MASK></PSOC0>
<EUDR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xCE</MEM_ADDR>
<EUDR0_MASK>0x01</EUDR0_MASK><EUDR1_MASK>0x02</EUDR1_MASK><EUDR2_MASK>0x04</EUDR2_MASK><EUDR3_MASK>0x08</EUDR3_MASK><EUDR4_MASK>0x10</EUDR4_MASK><EUDR5_MASK>0x20</EUDR5_MASK><EUDR6_MASK>0x40</EUDR6_MASK><EUDR7_MASK>0x80</EUDR7_MASK></EUDR>
<MUBRRH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xCD</MEM_ADDR>
<MUBRR8_MASK>0x01</MUBRR8_MASK><MUBRR9_MASK>0x02</MUBRR9_MASK><MUBRR10_MASK>0x04</MUBRR10_MASK><MUBRR11_MASK>0x08</MUBRR11_MASK><MUBRR12_MASK>0x10</MUBRR12_MASK><MUBRR13_MASK>0x20</MUBRR13_MASK><MUBRR14_MASK>0x40</MUBRR14_MASK><MUBRR15_MASK>0x80</MUBRR15_MASK></MUBRRH>
<MUBRRL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xCC</MEM_ADDR>
<MUBRR0_MASK>0x01</MUBRR0_MASK><MUBRR1_MASK>0x02</MUBRR1_MASK><MUBRR2_MASK>0x04</MUBRR2_MASK><MUBRR3_MASK>0x08</MUBRR3_MASK><MUBRR4_MASK>0x10</MUBRR4_MASK><MUBRR5_MASK>0x20</MUBRR5_MASK><MUBRR6_MASK>0x40</MUBRR6_MASK><MUBRR7_MASK>0x80</MUBRR7_MASK></MUBRRL>
<EUCSRC>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xCA</MEM_ADDR>
<STP0_MASK>0x01</STP0_MASK><STP1_MASK>0x02</STP1_MASK><F1617_MASK>0x04</F1617_MASK><FEM_MASK>0x08</FEM_MASK></EUCSRC>
<EUCSRB>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC9</MEM_ADDR>
<BODR_MASK>0x01</BODR_MASK><EMCH_MASK>0x02</EMCH_MASK><EUSBS_MASK>0x08</EUSBS_MASK><EUSART_MASK>0x10</EUSART_MASK></EUCSRB>
<EUCSRA>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC8</MEM_ADDR>
<URxS0_MASK>0x01</URxS0_MASK><URxS1_MASK>0x02</URxS1_MASK><URxS2_MASK>0x04</URxS2_MASK><URxS3_MASK>0x08</URxS3_MASK><UTxS0_MASK>0x10</UTxS0_MASK><UTxS1_MASK>0x20</UTxS1_MASK><UTxS2_MASK>0x40</UTxS2_MASK><UTxS3_MASK>0x80</UTxS3_MASK></EUCSRA>
<UDR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC6</MEM_ADDR>
<UDR0_MASK>0x01</UDR0_MASK><UDR1_MASK>0x02</UDR1_MASK><UDR2_MASK>0x04</UDR2_MASK><UDR3_MASK>0x08</UDR3_MASK><UDR4_MASK>0x10</UDR4_MASK><UDR5_MASK>0x20</UDR5_MASK><UDR6_MASK>0x40</UDR6_MASK><UDR7_MASK>0x80</UDR7_MASK></UDR>
<UBRRH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC5</MEM_ADDR>
<UBRR8_MASK>0x01</UBRR8_MASK><UBRR9_MASK>0x02</UBRR9_MASK><UBRR10_MASK>0x04</UBRR10_MASK><UBRR11_MASK>0x08</UBRR11_MASK></UBRRH>
<UBRRL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC4</MEM_ADDR>
<UBRR0_MASK>0x01</UBRR0_MASK><UBRR1_MASK>0x02</UBRR1_MASK><UBRR2_MASK>0x04</UBRR2_MASK><UBRR3_MASK>0x08</UBRR3_MASK><UBRR4_MASK>0x10</UBRR4_MASK><UBRR5_MASK>0x20</UBRR5_MASK><UBRR6_MASK>0x40</UBRR6_MASK><UBRR7_MASK>0x80</UBRR7_MASK></UBRRL>
<UCSRC>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC2</MEM_ADDR>
<UCPOL_MASK>0x01</UCPOL_MASK><UCSZ0_MASK>0x02</UCSZ0_MASK><UCSZ1_MASK>0x04</UCSZ1_MASK><USBS_MASK>0x08</USBS_MASK><UPM0_MASK>0x10</UPM0_MASK><UPM1_MASK>0x20</UPM1_MASK><UMSEL0_MASK>0x40</UMSEL0_MASK></UCSRC>
<UCSRB>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC1</MEM_ADDR>
<TXB8_MASK>0x01</TXB8_MASK><RXB8_MASK>0x02</RXB8_MASK><UCSZ2_MASK>0x04</UCSZ2_MASK><TXEN_MASK>0x08</TXEN_MASK><RXEN_MASK>0x10</RXEN_MASK><UDRIE_MASK>0x20</UDRIE_MASK><TXCIE_MASK>0x40</TXCIE_MASK><RXCIE_MASK>0x80</RXCIE_MASK></UCSRB>
<UCSRA>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC0</MEM_ADDR>
<MPCM_MASK>0x01</MPCM_MASK><U2X_MASK>0x02</U2X_MASK><UPE_MASK>0x04</UPE_MASK><DOR_MASK>0x08</DOR_MASK><FE_MASK>0x10</FE_MASK><UDRE_MASK>0x20</UDRE_MASK><TXC_MASK>0x40</TXC_MASK><RXC_MASK>0x80</RXC_MASK></UCSRA>
<AC2CON>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AF</MEM_ADDR>
<AC2M0_MASK>0x01</AC2M0_MASK><AC2M1_MASK>0x02</AC2M1_MASK><AC2M2_MASK>0x04</AC2M2_MASK><AC2IS0_MASK>0x10</AC2IS0_MASK><AC2IS1_MASK>0x20</AC2IS1_MASK><AC2IE_MASK>0x40</AC2IE_MASK><AC2EN_MASK>0x80</AC2EN_MASK></AC2CON>
<AC1CON>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AE</MEM_ADDR>
<AC1M0_MASK>0x01</AC1M0_MASK><AC1M1_MASK>0x02</AC1M1_MASK><AC1M2_MASK>0x04</AC1M2_MASK><AC1ICE_MASK>0x08</AC1ICE_MASK><AC1IS0_MASK>0x10</AC1IS0_MASK><AC1IS1_MASK>0x20</AC1IS1_MASK><AC1IE_MASK>0x40</AC1IE_MASK><AC1EN_MASK>0x80</AC1EN_MASK></AC1CON>
<AC0CON>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AD</MEM_ADDR>
<AC0M0_MASK>0x01</AC0M0_MASK><AC0M1_MASK>0x02</AC0M1_MASK><AC0M2_MASK>0x04</AC0M2_MASK><AC0IS0_MASK>0x10</AC0IS0_MASK><AC0IS1_MASK>0x20</AC0IS1_MASK><AC0IE_MASK>0x40</AC0IE_MASK><AC0EN_MASK>0x80</AC0EN_MASK></AC0CON>
<DACH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AC</MEM_ADDR>
<DACH0_MASK>0x01</DACH0_MASK><DACH1_MASK>0x02</DACH1_MASK><DACH2_MASK>0x04</DACH2_MASK><DACH3_MASK>0x08</DACH3_MASK><DACH4_MASK>0x10</DACH4_MASK><DACH5_MASK>0x20</DACH5_MASK><DACH6_MASK>0x40</DACH6_MASK><DACH7_MASK>0x80</DACH7_MASK></DACH>
<DACL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AB</MEM_ADDR>
<DACL0_MASK>0x01</DACL0_MASK><DACL1_MASK>0x02</DACL1_MASK><DACL2_MASK>0x04</DACL2_MASK><DACL3_MASK>0x08</DACL3_MASK><DACL4_MASK>0x10</DACL4_MASK><DACL5_MASK>0x20</DACL5_MASK><DACL6_MASK>0x40</DACL6_MASK><DACL7_MASK>0x80</DACL7_MASK></DACL>
<DACON>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AA</MEM_ADDR>
<DAEN_MASK>0x01</DAEN_MASK><DAOE_MASK>0x02</DAOE_MASK><DALA_MASK>0x04</DALA_MASK><DATS0_MASK>0x10</DATS0_MASK><DATS1_MASK>0x20</DATS1_MASK><DATS2_MASK>0x40</DATS2_MASK><DAATE_MASK>0x80</DAATE_MASK></DACON>
<PIM2>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A5</MEM_ADDR>
<PEOPE2_MASK>0x01</PEOPE2_MASK><PEVE2A_MASK>0x08</PEVE2A_MASK><PEVE2B_MASK>0x10</PEVE2B_MASK><PSEIE2_MASK>0x20</PSEIE2_MASK></PIM2>
<PIFR2>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A4</MEM_ADDR>
<PEOP2_MASK>0x01</PEOP2_MASK><PRN20_MASK>0x02</PRN20_MASK><PRN21_MASK>0x04</PRN21_MASK><PEV2A_MASK>0x08</PEV2A_MASK><PEV2B_MASK>0x10</PEV2B_MASK><PSEI2_MASK>0x20</PSEI2_MASK></PIFR2>
<PIM1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A3</MEM_ADDR>
</PIM1>
<PIFR1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A2</MEM_ADDR>
</PIFR1>
<PIM0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A1</MEM_ADDR>
<PEOPE0_MASK>0x01</PEOPE0_MASK><PEVE0A_MASK>0x08</PEVE0A_MASK><PEVE0B_MASK>0x10</PEVE0B_MASK><PSEIE0_MASK>0x20</PSEIE0_MASK></PIM0>
<PIFR0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A0</MEM_ADDR>
<PEOP0_MASK>0x01</PEOP0_MASK><PRN00_MASK>0x02</PRN00_MASK><PRN01_MASK>0x04</PRN01_MASK><PEV0A_MASK>0x08</PEV0A_MASK><PEV0B_MASK>0x10</PEV0B_MASK><PSEI0_MASK>0x20</PSEI0_MASK></PIFR0>
<OCR1BH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$8B</MEM_ADDR>
<OCR1BH0_MASK>0x01</OCR1BH0_MASK><OCR1BH1_MASK>0x02</OCR1BH1_MASK><OCR1BH2_MASK>0x04</OCR1BH2_MASK><OCR1BH3_MASK>0x08</OCR1BH3_MASK><OCR1BH4_MASK>0x10</OCR1BH4_MASK><OCR1BH5_MASK>0x20</OCR1BH5_MASK><OCR1BH6_MASK>0x40</OCR1BH6_MASK><OCR1BH7_MASK>0x80</OCR1BH7_MASK></OCR1BH>
<OCR1BL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$8A</MEM_ADDR>
<OCR1BL0_MASK>0x01</OCR1BL0_MASK><OCR1BL1_MASK>0x02</OCR1BL1_MASK><OCR1BL2_MASK>0x04</OCR1BL2_MASK><OCR1BL3_MASK>0x08</OCR1BL3_MASK><OCR1BL4_MASK>0x10</OCR1BL4_MASK><OCR1BL5_MASK>0x20</OCR1BL5_MASK><OCR1BL6_MASK>0x40</OCR1BL6_MASK><OCR1BL7_MASK>0x80</OCR1BL7_MASK></OCR1BL>
<OCR1AH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$89</MEM_ADDR>
<OCR1AH0_MASK>0x01</OCR1AH0_MASK><OCR1AH1_MASK>0x02</OCR1AH1_MASK><OCR1AH2_MASK>0x04</OCR1AH2_MASK><OCR1AH3_MASK>0x08</OCR1AH3_MASK><OCR1AH4_MASK>0x10</OCR1AH4_MASK><OCR1AH5_MASK>0x20</OCR1AH5_MASK><OCR1AH6_MASK>0x40</OCR1AH6_MASK><OCR1AH7_MASK>0x80</OCR1AH7_MASK></OCR1AH>
<OCR1AL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$88</MEM_ADDR>
<OCR1AL0_MASK>0x01</OCR1AL0_MASK><OCR1AL1_MASK>0x02</OCR1AL1_MASK><OCR1AL2_MASK>0x04</OCR1AL2_MASK><OCR1AL3_MASK>0x08</OCR1AL3_MASK><OCR1AL4_MASK>0x10</OCR1AL4_MASK><OCR1AL5_MASK>0x20</OCR1AL5_MASK><OCR1AL6_MASK>0x40</OCR1AL6_MASK><OCR1AL7_MASK>0x80</OCR1AL7_MASK></OCR1AL>
<ICR1H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$87</MEM_ADDR>
<ICR1H0_MASK>0x01</ICR1H0_MASK><ICR1H1_MASK>0x02</ICR1H1_MASK><ICR1H2_MASK>0x04</ICR1H2_MASK><ICR1H3_MASK>0x08</ICR1H3_MASK><ICR1H4_MASK>0x10</ICR1H4_MASK><ICR1H5_MASK>0x20</ICR1H5_MASK><ICR1H6_MASK>0x40</ICR1H6_MASK><ICR1H7_MASK>0x80</ICR1H7_MASK></ICR1H>
<ICR1L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$86</MEM_ADDR>
<ICR1L0_MASK>0x01</ICR1L0_MASK><ICR1L1_MASK>0x02</ICR1L1_MASK><ICR1L2_MASK>0x04</ICR1L2_MASK><ICR1L3_MASK>0x08</ICR1L3_MASK><ICR1L4_MASK>0x10</ICR1L4_MASK><ICR1L5_MASK>0x20</ICR1L5_MASK><ICR1L6_MASK>0x40</ICR1L6_MASK><ICR1L7_MASK>0x80</ICR1L7_MASK></ICR1L>
<TCNT1H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$85</MEM_ADDR>
<TCNT1H0_MASK>0x01</TCNT1H0_MASK><TCNT1H1_MASK>0x02</TCNT1H1_MASK><TCNT1H2_MASK>0x04</TCNT1H2_MASK><TCNT1H3_MASK>0x08</TCNT1H3_MASK><TCNT1H4_MASK>0x10</TCNT1H4_MASK><TCNT1H5_MASK>0x20</TCNT1H5_MASK><TCNT1H6_MASK>0x40</TCNT1H6_MASK><TCNT1H7_MASK>0x80</TCNT1H7_MASK></TCNT1H>
<TCNT1L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$84</MEM_ADDR>
<TCNT1L0_MASK>0x01</TCNT1L0_MASK><TCNT1L1_MASK>0x02</TCNT1L1_MASK><TCNT1L2_MASK>0x04</TCNT1L2_MASK><TCNT1L3_MASK>0x08</TCNT1L3_MASK><TCNT1L4_MASK>0x10</TCNT1L4_MASK><TCNT1L5_MASK>0x20</TCNT1L5_MASK><TCNT1L6_MASK>0x40</TCNT1L6_MASK><TCNT1L7_MASK>0x80</TCNT1L7_MASK></TCNT1L>
<TCCR1C>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$82</MEM_ADDR>
<FOC1B_MASK>0x40</FOC1B_MASK><FOC1A_MASK>0x80</FOC1A_MASK></TCCR1C>
<TCCR1B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$81</MEM_ADDR>
<CS10_MASK>0x01</CS10_MASK><CS11_MASK>0x02</CS11_MASK><CS12_MASK>0x04</CS12_MASK><WGM12_MASK>0x08</WGM12_MASK><WGM13_MASK>0x10</WGM13_MASK><ICES1_MASK>0x40</ICES1_MASK><ICNC1_MASK>0x80</ICNC1_MASK></TCCR1B>
<TCCR1A>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$80</MEM_ADDR>
<WGM10_MASK>0x01</WGM10_MASK><WGM11_MASK>0x02</WGM11_MASK><COM1B0_MASK>0x10</COM1B0_MASK><COM1B1_MASK>0x20</COM1B1_MASK><COM1A0_MASK>0x40</COM1A0_MASK><COM1A1_MASK>0x80</COM1A1_MASK></TCCR1A>
<DIDR1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7F</MEM_ADDR>
<ADC8D_MASK>0x01</ADC8D_MASK><ADC9D_MASK>0x02</ADC9D_MASK><ADC10D_MASK>0x04</ADC10D_MASK><AMP0ND_MASK>0x08</AMP0ND_MASK><AMP0PD_MASK>0x10</AMP0PD_MASK><ACMP0D_MASK>0x20</ACMP0D_MASK></DIDR1>
<DIDR0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7E</MEM_ADDR>
<ADC0D_MASK>0x01</ADC0D_MASK><ADC1D_MASK>0x02</ADC1D_MASK><ADC2D_MASK>0x04</ADC2D_MASK><ADC3D_MASK>0x08</ADC3D_MASK><ADC4D_MASK>0x10</ADC4D_MASK><ADC5D_MASK>0x20</ADC5D_MASK><ADC6D_MASK>0x40</ADC6D_MASK><ADC7D_MASK>0x80</ADC7D_MASK></DIDR0>
<ADMUX>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7C</MEM_ADDR>
<MUX0_MASK>0x01</MUX0_MASK><MUX1_MASK>0x02</MUX1_MASK><MUX2_MASK>0x04</MUX2_MASK><MUX3_MASK>0x08</MUX3_MASK><ADLAR_MASK>0x20</ADLAR_MASK><REFS0_MASK>0x40</REFS0_MASK><REFS1_MASK>0x80</REFS1_MASK></ADMUX>
<ADCSRB>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7B</MEM_ADDR>
<ADTS0_MASK>0x01</ADTS0_MASK><ADTS1_MASK>0x02</ADTS1_MASK><ADTS2_MASK>0x04</ADTS2_MASK><ADTS3_MASK>0x08</ADTS3_MASK><ADASCR_MASK>0x10</ADASCR_MASK><ADHSM_MASK>0x80</ADHSM_MASK></ADCSRB>
<ADCSRA>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7A</MEM_ADDR>
<ADPS0_MASK>0x01</ADPS0_MASK><ADPS1_MASK>0x02</ADPS1_MASK><ADPS2_MASK>0x04</ADPS2_MASK><ADIE_MASK>0x08</ADIE_MASK><ADIF_MASK>0x10</ADIF_MASK><ADATE_MASK>0x20</ADATE_MASK><ADSC_MASK>0x40</ADSC_MASK><ADEN_MASK>0x80</ADEN_MASK></ADCSRA>
<ADCH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$79</MEM_ADDR>
<ADCH0_MASK>0x01</ADCH0_MASK><ADCH1_MASK>0x02</ADCH1_MASK><ADCH2_MASK>0x04</ADCH2_MASK><ADCH3_MASK>0x08</ADCH3_MASK><ADCH4_MASK>0x10</ADCH4_MASK><ADCH5_MASK>0x20</ADCH5_MASK><ADCH6_MASK>0x40</ADCH6_MASK><ADCH7_MASK>0x80</ADCH7_MASK></ADCH>
<ADCL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$78</MEM_ADDR>
<ADCL0_MASK>0x01</ADCL0_MASK><ADCL1_MASK>0x02</ADCL1_MASK><ADCL2_MASK>0x04</ADCL2_MASK><ADCL3_MASK>0x08</ADCL3_MASK><ADCL4_MASK>0x10</ADCL4_MASK><ADCL5_MASK>0x20</ADCL5_MASK><ADCL6_MASK>0x40</ADCL6_MASK><ADCL7_MASK>0x80</ADCL7_MASK></ADCL>
<AMP1CSR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$77</MEM_ADDR>
</AMP1CSR>
<AMP0CSR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$76</MEM_ADDR>
</AMP0CSR>
<TIMSK1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6F</MEM_ADDR>
<TOIE1_MASK>0x01</TOIE1_MASK><OCIE1A_MASK>0x02</OCIE1A_MASK><OCIE1B_MASK>0x04</OCIE1B_MASK><ICIE1_MASK>0x20</ICIE1_MASK></TIMSK1>
<TIMSK0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6E</MEM_ADDR>
<TOIE0_MASK>0x01</TOIE0_MASK><OCIE0A_MASK>0x02</OCIE0A_MASK><OCIE0B_MASK>0x04</OCIE0B_MASK></TIMSK0>
<EICRA>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$69</MEM_ADDR>
<ISC00_MASK>0x01</ISC00_MASK><ISC01_MASK>0x02</ISC01_MASK><ISC10_MASK>0x04</ISC10_MASK><ISC11_MASK>0x08</ISC11_MASK><ISC20_MASK>0x10</ISC20_MASK><ISC21_MASK>0x20</ISC21_MASK></EICRA>
<OSCCAL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$66</MEM_ADDR>
<CAL0_MASK>0x01</CAL0_MASK><CAL1_MASK>0x02</CAL1_MASK><CAL2_MASK>0x04</CAL2_MASK><CAL3_MASK>0x08</CAL3_MASK><CAL4_MASK>0x10</CAL4_MASK><CAL5_MASK>0x20</CAL5_MASK><CAL6_MASK>0x40</CAL6_MASK></OSCCAL>
<PRR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$64</MEM_ADDR>
</PRR>
<CLKPR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$61</MEM_ADDR>
<CLKPS0_MASK>0x01</CLKPS0_MASK><CLKPS1_MASK>0x02</CLKPS1_MASK><CLKPS2_MASK>0x04</CLKPS2_MASK><CLKPS3_MASK>0x08</CLKPS3_MASK><CLKPCE_MASK>0x80</CLKPCE_MASK></CLKPR>
<WDTCSR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$60</MEM_ADDR>
<WDP0_MASK>0x01</WDP0_MASK><WDP1_MASK>0x02</WDP1_MASK><WDP2_MASK>0x04</WDP2_MASK><WDE_MASK>0x08</WDE_MASK><WDCE_MASK>0x10</WDCE_MASK><WDP3_MASK>0x20</WDP3_MASK><WDIE_MASK>0x40</WDIE_MASK><WDIF_MASK>0x80</WDIF_MASK></WDTCSR>
<SREG>
<IO_ADDR>$3F</IO_ADDR>
<MEM_ADDR>$5F</MEM_ADDR>
<C_MASK>0x01</C_MASK><Z_MASK>0x02</Z_MASK><N_MASK>0x04</N_MASK><V_MASK>0x08</V_MASK><S_MASK>0x10</S_MASK><H_MASK>0x20</H_MASK><T_MASK>0x40</T_MASK><I_MASK>0x80</I_MASK></SREG>
<SPH>
<IO_ADDR>$3E</IO_ADDR>
<MEM_ADDR>$5E</MEM_ADDR>
<SP8_MASK>0x01</SP8_MASK><SP9_MASK>0x02</SP9_MASK><SP10_MASK>0x04</SP10_MASK><SP11_MASK>0x08</SP11_MASK><SP12_MASK>0x10</SP12_MASK><SP13_MASK>0x20</SP13_MASK><SP14_MASK>0x40</SP14_MASK><SP15_MASK>0x80</SP15_MASK></SPH>
<SPL>
<IO_ADDR>$3D</IO_ADDR>
<MEM_ADDR>$5D</MEM_ADDR>
<SP0_MASK>0x01</SP0_MASK><SP1_MASK>0x02</SP1_MASK><SP2_MASK>0x04</SP2_MASK><SP3_MASK>0x08</SP3_MASK><SP4_MASK>0x10</SP4_MASK><SP5_MASK>0x20</SP5_MASK><SP6_MASK>0x40</SP6_MASK><SP7_MASK>0x80</SP7_MASK></SPL>
<SPMCSR>
<IO_ADDR>$37</IO_ADDR>
<MEM_ADDR>$57</MEM_ADDR>
<SPMEN_MASK>0x01</SPMEN_MASK><PGERS_MASK>0x02</PGERS_MASK><PGWRT_MASK>0x04</PGWRT_MASK><BLBSET_MASK>0x08</BLBSET_MASK><RWWSRE_MASK>0x10</RWWSRE_MASK><RWWSB_MASK>0x40</RWWSB_MASK><SPMIE_MASK>0x80</SPMIE_MASK></SPMCSR>
<MCUCR>
<IO_ADDR>$35</IO_ADDR>
<MEM_ADDR>$55</MEM_ADDR>
<IVCE_MASK>0x01</IVCE_MASK><IVSEL_MASK>0x02</IVSEL_MASK><PUD_MASK>0x10</PUD_MASK><SPIPS_MASK>0x80</SPIPS_MASK></MCUCR>
<MCUSR>
<IO_ADDR>$34</IO_ADDR>
<MEM_ADDR>$54</MEM_ADDR>
<PORF_MASK>0x01</PORF_MASK><EXTRF_MASK>0x02</EXTRF_MASK><BORF_MASK>0x04</BORF_MASK><WDRF_MASK>0x08</WDRF_MASK></MCUSR>
<SMCR>
<IO_ADDR>$33</IO_ADDR>
<MEM_ADDR>$53</MEM_ADDR>
<SE_MASK>0x01</SE_MASK><SM0_MASK>0x02</SM0_MASK><SM1_MASK>0x04</SM1_MASK><SM2_MASK>0x08</SM2_MASK></SMCR>
<ACSR>
<IO_ADDR>$30</IO_ADDR>
<MEM_ADDR>$50</MEM_ADDR>
</ACSR>
<SPDR>
<IO_ADDR>$2E</IO_ADDR>
<MEM_ADDR>$4E</MEM_ADDR>
<SPDR0_MASK>0x01</SPDR0_MASK><SPDR1_MASK>0x02</SPDR1_MASK><SPDR2_MASK>0x04</SPDR2_MASK><SPDR3_MASK>0x08</SPDR3_MASK><SPDR4_MASK>0x10</SPDR4_MASK><SPDR5_MASK>0x20</SPDR5_MASK><SPDR6_MASK>0x40</SPDR6_MASK><SPDR7_MASK>0x80</SPDR7_MASK></SPDR>
<SPSR>
<IO_ADDR>$2D</IO_ADDR>
<MEM_ADDR>$4D</MEM_ADDR>
<SPI2X_MASK>0x01</SPI2X_MASK><WCOL_MASK>0x40</WCOL_MASK><SPIF_MASK>0x80</SPIF_MASK></SPSR>
<SPCR>
<IO_ADDR>$2C</IO_ADDR>
<MEM_ADDR>$4C</MEM_ADDR>
<SPR0_MASK>0x01</SPR0_MASK><SPR1_MASK>0x02</SPR1_MASK><CPHA_MASK>0x04</CPHA_MASK><CPOL_MASK>0x08</CPOL_MASK><MSTR_MASK>0x10</MSTR_MASK><DORD_MASK>0x20</DORD_MASK><SPE_MASK>0x40</SPE_MASK><SPIE_MASK>0x80</SPIE_MASK></SPCR>
<PLLCSR>
<IO_ADDR>$29</IO_ADDR>
<MEM_ADDR>$49</MEM_ADDR>
<PLOCK_MASK>0x01</PLOCK_MASK><PLLE_MASK>0x02</PLLE_MASK><PLLF_MASK>0x04</PLLF_MASK></PLLCSR>
<OCR0B>
<IO_ADDR>$28</IO_ADDR>
<MEM_ADDR>$48</MEM_ADDR>
<OCR0_0_MASK>0x01</OCR0_0_MASK><OCR0_1_MASK>0x02</OCR0_1_MASK><OCR0_2_MASK>0x04</OCR0_2_MASK><OCR0_3_MASK>0x08</OCR0_3_MASK><OCR0_4_MASK>0x10</OCR0_4_MASK><OCR0_5_MASK>0x20</OCR0_5_MASK><OCR0_6_MASK>0x40</OCR0_6_MASK><OCR0_7_MASK>0x80</OCR0_7_MASK></OCR0B>
<OCR0A>
<IO_ADDR>$27</IO_ADDR>
<MEM_ADDR>$47</MEM_ADDR>
<OCR0_0_MASK>0x01</OCR0_0_MASK><OCR0_1_MASK>0x02</OCR0_1_MASK><OCR0_2_MASK>0x04</OCR0_2_MASK><OCR0_3_MASK>0x08</OCR0_3_MASK><OCR0_4_MASK>0x10</OCR0_4_MASK><OCR0_5_MASK>0x20</OCR0_5_MASK><OCR0_6_MASK>0x40</OCR0_6_MASK><OCR0_7_MASK>0x80</OCR0_7_MASK></OCR0A>
<TCNT0>
<IO_ADDR>$26</IO_ADDR>
<MEM_ADDR>$46</MEM_ADDR>
<TCNT0_0_MASK>0x01</TCNT0_0_MASK><TCNT0_1_MASK>0x02</TCNT0_1_MASK><TCNT0_2_MASK>0x04</TCNT0_2_MASK><TCNT0_3_MASK>0x08</TCNT0_3_MASK><TCNT0_4_MASK>0x10</TCNT0_4_MASK><TCNT0_5_MASK>0x20</TCNT0_5_MASK><TCNT0_6_MASK>0x40</TCNT0_6_MASK><TCNT0_7_MASK>0x80</TCNT0_7_MASK></TCNT0>
<TCCR0B>
<IO_ADDR>$25</IO_ADDR>
<MEM_ADDR>$45</MEM_ADDR>
<CS00_MASK>0x01</CS00_MASK><CS01_MASK>0x02</CS01_MASK><CS02_MASK>0x04</CS02_MASK><WGM02_MASK>0x08</WGM02_MASK><FOC0B_MASK>0x40</FOC0B_MASK><FOC0A_MASK>0x80</FOC0A_MASK></TCCR0B>
<TCCR0A>
<IO_ADDR>$24</IO_ADDR>
<MEM_ADDR>$44</MEM_ADDR>
<WGM00_MASK>0x01</WGM00_MASK><WGM01_MASK>0x02</WGM01_MASK><COM0B0_MASK>0x10</COM0B0_MASK><COM0B1_MASK>0x20</COM0B1_MASK><COM0A0_MASK>0x40</COM0A0_MASK><COM0A1_MASK>0x80</COM0A1_MASK></TCCR0A>
<GTCCR>
<IO_ADDR>$23</IO_ADDR>
<MEM_ADDR>$43</MEM_ADDR>
<PSR10_MASK>0x01</PSR10_MASK><ICPSEL1_MASK>0x40</ICPSEL1_MASK><TSM_MASK>0x80</TSM_MASK><PSRSYNC_MASK>0x01</PSRSYNC_MASK></GTCCR>
<EEARH>
<IO_ADDR>$22</IO_ADDR>
<MEM_ADDR>$42</MEM_ADDR>
<EEAR8_MASK>0x01</EEAR8_MASK><EEAR9_MASK>0x02</EEAR9_MASK><EEAR10_MASK>0x04</EEAR10_MASK><EEAR11_MASK>0x08</EEAR11_MASK></EEARH>
<EEARL>
<IO_ADDR>$21</IO_ADDR>
<MEM_ADDR>$41</MEM_ADDR>
<EEARL0_MASK>0x01</EEARL0_MASK><EEARL1_MASK>0x02</EEARL1_MASK><EEARL2_MASK>0x04</EEARL2_MASK><EEARL3_MASK>0x08</EEARL3_MASK><EEARL4_MASK>0x10</EEARL4_MASK><EEARL5_MASK>0x20</EEARL5_MASK><EEARL6_MASK>0x40</EEARL6_MASK><EEARL7_MASK>0x80</EEARL7_MASK></EEARL>
<EEDR>
<IO_ADDR>$20</IO_ADDR>
<MEM_ADDR>$40</MEM_ADDR>
<EEDR0_MASK>0x01</EEDR0_MASK><EEDR1_MASK>0x02</EEDR1_MASK><EEDR2_MASK>0x04</EEDR2_MASK><EEDR3_MASK>0x08</EEDR3_MASK><EEDR4_MASK>0x10</EEDR4_MASK><EEDR5_MASK>0x20</EEDR5_MASK><EEDR6_MASK>0x40</EEDR6_MASK><EEDR7_MASK>0x80</EEDR7_MASK></EEDR>
<EECR>
<IO_ADDR>$1F</IO_ADDR>
<MEM_ADDR>$3F</MEM_ADDR>
<EERE_MASK>0x01</EERE_MASK><EEWE_MASK>0x02</EEWE_MASK><EEMWE_MASK>0x04</EEMWE_MASK><EERIE_MASK>0x08</EERIE_MASK><EEPM0_MASK>0x10</EEPM0_MASK><EEPM1_MASK>0x20</EEPM1_MASK></EECR>
<GPIOR0>
<IO_ADDR>$1E</IO_ADDR>
<MEM_ADDR>$3E</MEM_ADDR>
<GPIOR00_MASK>0x01</GPIOR00_MASK><GPIOR01_MASK>0x02</GPIOR01_MASK><GPIOR02_MASK>0x04</GPIOR02_MASK><GPIOR03_MASK>0x08</GPIOR03_MASK><GPIOR04_MASK>0x10</GPIOR04_MASK><GPIOR05_MASK>0x20</GPIOR05_MASK><GPIOR06_MASK>0x40</GPIOR06_MASK><GPIOR07_MASK>0x80</GPIOR07_MASK></GPIOR0>
<EIMSK>
<IO_ADDR>$1D</IO_ADDR>
<MEM_ADDR>$3D</MEM_ADDR>
<INT0_MASK>0x01</INT0_MASK><INT1_MASK>0x02</INT1_MASK><INT2_MASK>0x04</INT2_MASK></EIMSK>
<EIFR>
<IO_ADDR>$1C</IO_ADDR>
<MEM_ADDR>$3C</MEM_ADDR>
<INTF0_MASK>0x01</INTF0_MASK><INTF1_MASK>0x02</INTF1_MASK><INTF2_MASK>0x04</INTF2_MASK></EIFR>
<GPIOR3>
<IO_ADDR>$1B</IO_ADDR>
<MEM_ADDR>$3B</MEM_ADDR>
<GPIOR30_MASK>0x01</GPIOR30_MASK><GPIOR31_MASK>0x02</GPIOR31_MASK><GPIOR32_MASK>0x04</GPIOR32_MASK><GPIOR33_MASK>0x08</GPIOR33_MASK><GPIOR34_MASK>0x10</GPIOR34_MASK><GPIOR35_MASK>0x20</GPIOR35_MASK><GPIOR36_MASK>0x40</GPIOR36_MASK><GPIOR37_MASK>0x80</GPIOR37_MASK></GPIOR3>
<GPIOR2>
<IO_ADDR>$1A</IO_ADDR>
<MEM_ADDR>$3A</MEM_ADDR>
<GPIOR20_MASK>0x01</GPIOR20_MASK><GPIOR21_MASK>0x02</GPIOR21_MASK><GPIOR22_MASK>0x04</GPIOR22_MASK><GPIOR23_MASK>0x08</GPIOR23_MASK><GPIOR24_MASK>0x10</GPIOR24_MASK><GPIOR25_MASK>0x20</GPIOR25_MASK><GPIOR26_MASK>0x40</GPIOR26_MASK><GPIOR27_MASK>0x80</GPIOR27_MASK></GPIOR2>
<GPIOR1>
<IO_ADDR>$19</IO_ADDR>
<MEM_ADDR>$39</MEM_ADDR>
<GPIOR10_MASK>0x01</GPIOR10_MASK><GPIOR11_MASK>0x02</GPIOR11_MASK><GPIOR12_MASK>0x04</GPIOR12_MASK><GPIOR13_MASK>0x08</GPIOR13_MASK><GPIOR14_MASK>0x10</GPIOR14_MASK><GPIOR15_MASK>0x20</GPIOR15_MASK><GPIOR16_MASK>0x40</GPIOR16_MASK><GPIOR17_MASK>0x80</GPIOR17_MASK></GPIOR1>
<TIFR1>
<IO_ADDR>$16</IO_ADDR>
<MEM_ADDR>$36</MEM_ADDR>
<TOV1_MASK>0x01</TOV1_MASK><OCF1A_MASK>0x02</OCF1A_MASK><OCF1B_MASK>0x04</OCF1B_MASK><ICF1_MASK>0x20</ICF1_MASK></TIFR1>
<TIFR0>
<IO_ADDR>$15</IO_ADDR>
<MEM_ADDR>$35</MEM_ADDR>
<TOV0_MASK>0x01</TOV0_MASK><OCF0A_MASK>0x02</OCF0A_MASK><OCF0B_MASK>0x04</OCF0B_MASK></TIFR0>
<PORTE>
<IO_ADDR>$0E</IO_ADDR>
<MEM_ADDR>$2E</MEM_ADDR>
<PORTE0_MASK>0x01</PORTE0_MASK><PORTE1_MASK>0x02</PORTE1_MASK><PORTE2_MASK>0x04</PORTE2_MASK></PORTE>
<DDRE>
<IO_ADDR>$0D</IO_ADDR>
<MEM_ADDR>$2D</MEM_ADDR>
<DDE0_MASK>0x01</DDE0_MASK><DDE1_MASK>0x02</DDE1_MASK><DDE2_MASK>0x04</DDE2_MASK></DDRE>
<PINE>
<IO_ADDR>$0C</IO_ADDR>
<MEM_ADDR>$2C</MEM_ADDR>
<PINE0_MASK>0x01</PINE0_MASK><PINE1_MASK>0x02</PINE1_MASK><PINE2_MASK>0x04</PINE2_MASK></PINE>
<PORTD>
<IO_ADDR>$0B</IO_ADDR>
<MEM_ADDR>$2B</MEM_ADDR>
<PORTD0_MASK>0x01</PORTD0_MASK><PORTD1_MASK>0x02</PORTD1_MASK><PORTD2_MASK>0x04</PORTD2_MASK><PORTD3_MASK>0x08</PORTD3_MASK><PORTD4_MASK>0x10</PORTD4_MASK><PORTD5_MASK>0x20</PORTD5_MASK><PORTD6_MASK>0x40</PORTD6_MASK><PORTD7_MASK>0x80</PORTD7_MASK></PORTD>
<DDRD>
<IO_ADDR>$0A</IO_ADDR>
<MEM_ADDR>$2A</MEM_ADDR>
<DDD0_MASK>0x01</DDD0_MASK><DDD1_MASK>0x02</DDD1_MASK><DDD2_MASK>0x04</DDD2_MASK><DDD3_MASK>0x08</DDD3_MASK><DDD4_MASK>0x10</DDD4_MASK><DDD5_MASK>0x20</DDD5_MASK><DDD6_MASK>0x40</DDD6_MASK><DDD7_MASK>0x80</DDD7_MASK></DDRD>
<PIND>
<IO_ADDR>$09</IO_ADDR>
<MEM_ADDR>$29</MEM_ADDR>
<PIND0_MASK>0x01</PIND0_MASK><PIND1_MASK>0x02</PIND1_MASK><PIND2_MASK>0x04</PIND2_MASK><PIND3_MASK>0x08</PIND3_MASK><PIND4_MASK>0x10</PIND4_MASK><PIND5_MASK>0x20</PIND5_MASK><PIND6_MASK>0x40</PIND6_MASK><PIND7_MASK>0x80</PIND7_MASK></PIND>
<PORTC>
<IO_ADDR>$08</IO_ADDR>
<MEM_ADDR>$28</MEM_ADDR>
</PORTC>
<DDRC>
<IO_ADDR>$07</IO_ADDR>
<MEM_ADDR>$27</MEM_ADDR>
</DDRC>
<PINC>
<IO_ADDR>$06</IO_ADDR>
<MEM_ADDR>$26</MEM_ADDR>
</PINC>
<PORTB>
<IO_ADDR>$05</IO_ADDR>
<MEM_ADDR>$25</MEM_ADDR>
<PORTB0_MASK>0x01</PORTB0_MASK><PORTB1_MASK>0x02</PORTB1_MASK><PORTB2_MASK>0x04</PORTB2_MASK><PORTB3_MASK>0x08</PORTB3_MASK><PORTB4_MASK>0x10</PORTB4_MASK><PORTB5_MASK>0x20</PORTB5_MASK><PORTB6_MASK>0x40</PORTB6_MASK><PORTB7_MASK>0x80</PORTB7_MASK></PORTB>
<DDRB>
<IO_ADDR>$04</IO_ADDR>
<MEM_ADDR>$24</MEM_ADDR>
<DDB0_MASK>0x01</DDB0_MASK><DDB1_MASK>0x02</DDB1_MASK><DDB2_MASK>0x04</DDB2_MASK><DDB3_MASK>0x08</DDB3_MASK><DDB4_MASK>0x10</DDB4_MASK><DDB5_MASK>0x20</DDB5_MASK><DDB6_MASK>0x40</DDB6_MASK><DDB7_MASK>0x80</DDB7_MASK></DDRB>
<PINB>
<IO_ADDR>$03</IO_ADDR>
<MEM_ADDR>$23</MEM_ADDR>
<PINB0_MASK>0x01</PINB0_MASK><PINB1_MASK>0x02</PINB1_MASK><PINB2_MASK>0x04</PINB2_MASK><PINB3_MASK>0x08</PINB3_MASK><PINB4_MASK>0x10</PINB4_MASK><PINB5_MASK>0x20</PINB5_MASK><PINB6_MASK>0x40</PINB6_MASK><PINB7_MASK>0x80</PINB7_MASK></PINB>
</IO_MEMORY>
<BOOT_CONFIG>
<NRWW_START_ADDR>$C00</NRWW_START_ADDR>
<NRWW_STOP_ADDR>$FFF</NRWW_STOP_ADDR>
<RWW_START_ADDR>$0</RWW_START_ADDR>
<RWW_STOP_ADDR>$BFF</RWW_STOP_ADDR>
<PAGESIZE>32</PAGESIZE>
<BOOTSZMODE1>
<BOOTSIZE>128</BOOTSIZE>
<PAGES>4</PAGES>
<APPSTART>$0</APPSTART>
<BOOTSTART>$F80</BOOTSTART>
<BOOTRESET>$F80</BOOTRESET>
</BOOTSZMODE1>
<BOOTSZMODE2>
<BOOTSIZE>256</BOOTSIZE>
<PAGES>8</PAGES>
<APPSTART>$0</APPSTART>
<BOOTSTART>$F00</BOOTSTART>
<BOOTRESET>$F00</BOOTRESET>
</BOOTSZMODE2>
<BOOTSZMODE3>
<BOOTSIZE>512</BOOTSIZE>
<PAGES>16</PAGES>
<APPSTART>$0</APPSTART>
<BOOTSTART>$E00</BOOTSTART>
<BOOTRESET>$E00</BOOTRESET>
</BOOTSZMODE3>
<BOOTSZMODE4>
<BOOTSIZE>1024</BOOTSIZE>
<PAGES>32</PAGES>
<APPSTART>$0</APPSTART>
<BOOTSTART>$C00</BOOTSTART>
<BOOTRESET>$C00</BOOTRESET>
</BOOTSZMODE4>
</BOOT_CONFIG>
</MEMORY>
<INTERRUPT_VECTOR>
<NMB_VECTORS>32</NMB_VECTORS>
<ID>AVRSimInterrupt.SimInterrupt</ID>
<VECTOR1>
<PROGRAM_ADDRESS>$0000</PROGRAM_ADDRESS>
<SOURCE>RESET</SOURCE>
<DEFINITION>External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset</DEFINITION>
</VECTOR1>
<VECTOR2>
<PROGRAM_ADDRESS>$0001</PROGRAM_ADDRESS>
<SOURCE>PSC2 CAPT</SOURCE>
<DEFINITION>PSC2 Capture Event</DEFINITION>
</VECTOR2>
<VECTOR3>
<PROGRAM_ADDRESS>$0002</PROGRAM_ADDRESS>
<SOURCE>PSC2 EC</SOURCE>
<DEFINITION>PSC2 End Cycle</DEFINITION>
</VECTOR3>
<VECTOR4>
<PROGRAM_ADDRESS>$0003</PROGRAM_ADDRESS>
<SOURCE>PSC1 CAPT</SOURCE>
<DEFINITION>PSC1 Capture Event</DEFINITION>
</VECTOR4>
<VECTOR5>
<PROGRAM_ADDRESS>$0004</PROGRAM_ADDRESS>
<SOURCE>PSC1 EC</SOURCE>
<DEFINITION>PSC1 End Cycle</DEFINITION>
</VECTOR5>
<VECTOR6>
<PROGRAM_ADDRESS>$0005</PROGRAM_ADDRESS>
<SOURCE>PSC0 CAPT</SOURCE>
<DEFINITION>PSC0 Capture Event</DEFINITION>
</VECTOR6>
<VECTOR7>
<PROGRAM_ADDRESS>$0006</PROGRAM_ADDRESS>
<SOURCE>PSC0 EC</SOURCE>
<DEFINITION>PSC0 End Cycle</DEFINITION>
</VECTOR7>
<VECTOR8>
<PROGRAM_ADDRESS>$0007</PROGRAM_ADDRESS>
<SOURCE>ANALOG COMP 0</SOURCE>
<DEFINITION>Analog Comparator 0</DEFINITION>
</VECTOR8>
<VECTOR9>
<PROGRAM_ADDRESS>$0008</PROGRAM_ADDRESS>
<SOURCE>ANALOG COMP 1</SOURCE>
<DEFINITION>Analog Comparator 1</DEFINITION>
</VECTOR9>
<VECTOR10>
<PROGRAM_ADDRESS>$0009</PROGRAM_ADDRESS>
<SOURCE>ANALOG COMP 2</SOURCE>
<DEFINITION>Analog Comparator 2</DEFINITION>
</VECTOR10>
<VECTOR11>
<PROGRAM_ADDRESS>$000A</PROGRAM_ADDRESS>
<SOURCE>INT0</SOURCE>
<DEFINITION>External Interrupt Request 0</DEFINITION>
</VECTOR11>
<VECTOR12>
<PROGRAM_ADDRESS>$000B</PROGRAM_ADDRESS>
<SOURCE>TIMER1 CAPT</SOURCE>
<DEFINITION>Timer/Counter1 Capture Event</DEFINITION>
</VECTOR12>
<VECTOR13>
<PROGRAM_ADDRESS>$000C</PROGRAM_ADDRESS>
<SOURCE>TIMER1 COMPA</SOURCE>
<DEFINITION>Timer/Counter1 Compare Match A</DEFINITION>
</VECTOR13>
<VECTOR14>
<PROGRAM_ADDRESS>$000D</PROGRAM_ADDRESS>
<SOURCE>TIMER1 COMPB</SOURCE>
<DEFINITION>Timer/Counter Compare Match B</DEFINITION>
</VECTOR14>
<VECTOR15>
<PROGRAM_ADDRESS>$000E</PROGRAM_ADDRESS>
<SOURCE>RESERVED15</SOURCE>
<DEFINITION/>
<!--Spaceholder to ensure correct size of vector table in generated include file.-->
</VECTOR15>
<VECTOR16>
<PROGRAM_ADDRESS>$000F</PROGRAM_ADDRESS>
<SOURCE>TIMER1 OVF</SOURCE>
<DEFINITION>Timer/Counter1 Overflow</DEFINITION>
</VECTOR16>
<VECTOR17>
<PROGRAM_ADDRESS>$0010</PROGRAM_ADDRESS>
<SOURCE>TIMER0 COMP A</SOURCE>
<DEFINITION>Timer/Counter0 Compare Match A</DEFINITION>
</VECTOR17>
<VECTOR18>
<PROGRAM_ADDRESS>$0011</PROGRAM_ADDRESS>
<SOURCE>TIMER0 OVF</SOURCE>
<DEFINITION>Timer/Counter0 Overflow</DEFINITION>
</VECTOR18>
<VECTOR19>
<PROGRAM_ADDRESS>$0012</PROGRAM_ADDRESS>
<SOURCE>ADC</SOURCE>
<DEFINITION>ADC Conversion Complete</DEFINITION>
</VECTOR19>
<VECTOR20>
<PROGRAM_ADDRESS>$0013</PROGRAM_ADDRESS>
<SOURCE>INT1</SOURCE>
<DEFINITION>External Interrupt Request 1</DEFINITION>
</VECTOR20>
<VECTOR21>
<PROGRAM_ADDRESS>$0014</PROGRAM_ADDRESS>
<SOURCE>SPI, STC</SOURCE>
<DEFINITION>SPI Serial Transfer Complete</DEFINITION>
</VECTOR21>
<VECTOR22>
<PROGRAM_ADDRESS>$0015</PROGRAM_ADDRESS>
<SOURCE>USART, RX</SOURCE>
<DEFINITION>USART, Rx Complete</DEFINITION>
</VECTOR22>
<VECTOR23>
<PROGRAM_ADDRESS>$0016</PROGRAM_ADDRESS>
<SOURCE>USART, UDRE</SOURCE>
<DEFINITION>USART Data Register Empty</DEFINITION>
</VECTOR23>
<VECTOR24>
<PROGRAM_ADDRESS>$0017</PROGRAM_ADDRESS>
<SOURCE>USART, TX</SOURCE>
<DEFINITION>USART, Tx Complete</DEFINITION>
</VECTOR24>
<VECTOR25>
<PROGRAM_ADDRESS>$0018</PROGRAM_ADDRESS>
<SOURCE>INT2</SOURCE>
<DEFINITION>External Interrupt Request 2</DEFINITION>
</VECTOR25>
<VECTOR26>
<PROGRAM_ADDRESS>$0019</PROGRAM_ADDRESS>
<SOURCE>WDT</SOURCE>
<DEFINITION>Watchdog Timeout Interrupt</DEFINITION>
</VECTOR26>
<VECTOR27>
<PROGRAM_ADDRESS>$001A</PROGRAM_ADDRESS>
<SOURCE>EE READY</SOURCE>
<DEFINITION>EEPROM Ready</DEFINITION>
</VECTOR27>
<VECTOR28>
<PROGRAM_ADDRESS>$001B</PROGRAM_ADDRESS>
<SOURCE>TIMER0 COMPB</SOURCE>
<DEFINITION>Timer Counter 0 Compare Match B</DEFINITION>
</VECTOR28>
<VECTOR29>
<PROGRAM_ADDRESS>$001C</PROGRAM_ADDRESS>
<SOURCE>INT3</SOURCE>
<DEFINITION>External Interrupt Request 3</DEFINITION>
</VECTOR29>
<VECTOR30>
<PROGRAM_ADDRESS>$001D</PROGRAM_ADDRESS>
<SOURCE>RESERVED30</SOURCE>
<DEFINITION/>
<!--Spaceholder to ensure correct size of vector table in generated include file.-->
</VECTOR30>
<VECTOR31>
<PROGRAM_ADDRESS>$001E</PROGRAM_ADDRESS>
<SOURCE>RESERVED31</SOURCE>
<DEFINITION/>
<!--Spaceholder to ensure correct size of vector table in generated include file.-->
</VECTOR31>
<VECTOR32>
<PROGRAM_ADDRESS>$001F</PROGRAM_ADDRESS>
<SOURCE>SPM READY</SOURCE>
<DEFINITION>Store Program Memory Read</DEFINITION>
</VECTOR32>
</INTERRUPT_VECTOR>
<PACKAGE>
<PACKAGES>[SOIC]</PACKAGES>
<SOIC>
<NMB_PIN>24</NMB_PIN>
<PIN1>
<NAME>[PD0:PSCOUT00:XCK:SSA]</NAME>
<TEXT/>
</PIN1>
<PIN2>
<NAME>[PE0:RESET:OCD]</NAME>
<TEXT/>
</PIN2>
<PIN3>
<NAME>[PD1:PSCIN0:CLK0]</NAME>
<TEXT/>
</PIN3>
<PIN4>
<NAME>[PD2:PSCIN2:OC1A:MISO_A]</NAME>
<TEXT/>
</PIN4>
<PIN5>
<NAME>[PD3:TXD:DALI:OC0A:SS:MOSI_A]</NAME>
<TEXT/>
</PIN5>
<PIN6>
<NAME>[VCC]</NAME>
<TEXT/>
</PIN6>
<PIN7>
<NAME>[GND]</NAME>
<TEXT/>
</PIN7>
<PIN8>
<NAME>[PB0:MISO:PSCOUT20]</NAME>
<TEXT/>
</PIN8>
<PIN9>
<NAME>[PB1:MOSI:PSCOUT21]</NAME>
<TEXT/>
</PIN9>
<PIN10>
<NAME>[PE1:OC0B:XTAL1]</NAME>
<TEXT/>
</PIN10>
<PIN11>
<NAME>[PE2:ADC0:XTAL2]</NAME>
<TEXT/>
</PIN11>
<PIN12>
<NAME>[PD4:ADC1:RXD:DALI:ICP1:SCK_A]</NAME>
<TEXT/>
</PIN12>
<PIN13>
<NAME>[PD5:ADC2:ACMP2]</NAME>
<TEXT/>
</PIN13>
<PIN14>
<NAME>[PD6:ADC3:ACMPM:INT0]</NAME>
<TEXT/>
</PIN14>
<PIN15>
<NAME>[PD7:ACMP0]</NAME>
<TEXT/>
</PIN15>
<PIN16>
<NAME>[PB2:ADC5:INT1]</NAME>
<TEXT/>
</PIN16>
<PIN17>
<NAME>[AVCC]</NAME>
<TEXT/>
</PIN17>
<PIN18>
<NAME>[AGND]</NAME>
<TEXT/>
</PIN18>
<PIN19>
<NAME>[AREF]</NAME>
<TEXT/>
</PIN19>
<PIN20>
<NAME>[PB3:AMP0-]</NAME>
<TEXT/>
</PIN20>
<PIN21>
<NAME>[PB4:AMP0+]</NAME>
<TEXT/>
</PIN21>
<PIN22>
<NAME>[PB5:ADC6:INT2]</NAME>
<TEXT/>
</PIN22>
<PIN23>
<NAME>[PB6:ADC7:PSCOUT11:ICP1B]</NAME>
<TEXT/>
</PIN23>
<PIN24>
<NAME>[PB7:ADC4:PSCOUT01:SCK)</NAME>
<TEXT/>
</PIN24>
</SOIC>
</PACKAGE>
<PROGRAMMING>
<ISPInterface>
<FuseReadMask>0xff,0xdf,0xff</FuseReadMask>
<FuseProgMask>0xff,0xdf,0xff</FuseProgMask>
<FuseWarning>1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!</FuseWarning>
<FuseWarning>1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!</FuseWarning>
<FuseWarning>1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!</FuseWarning>
<FuseWarning>2,0x90,0x00,WARNING! These fuse settings will make the Parallel interface inaccessible!</FuseWarning>
</ISPInterface>
<HVInterface>
<FuseWarning>1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!</FuseWarning>
<FuseWarning>1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!</FuseWarning>
<FuseWarning>1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!</FuseWarning>
<FuseWarning>2,0x90,0x00,WARNING! These fuse settings will make the Parallel interface inaccessible!</FuseWarning>
</HVInterface>
<OscCal>
<OCEntry>0x00,8.0 MHz</OCEntry>
</OscCal>
<FlashPageSize>64</FlashPageSize>
<EepromPageSize>4</EepromPageSize>
</PROGRAMMING>
<FUSE>
<LIST>[LOW:HIGH:EXTENDED]</LIST>
<ID/>
<ICON/>
<TEXT/>
<LOW>
<NMB_FUSE_BITS>8</NMB_FUSE_BITS>
<FUSE7>
<NAME>CLKDIV8</NAME>
<TEXT>Divide clock by 8</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE7>
<FUSE6>
<NAME>CKOUT</NAME>
<TEXT>Oscillator output option</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE6>
<FUSE5>
<NAME>SUT1</NAME>
<TEXT>Select start-up time</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE5>
<FUSE4>
<NAME>SUT0</NAME>
<TEXT>Select start-up time</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE4>
<FUSE3>
<NAME>CKSEL3</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE3>
<FUSE2>
<NAME>CKSEL2</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE2>
<FUSE1>
<NAME>CKSEL1</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE1>
<FUSE0>
<NAME>CKSEL0</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE0>
<NMB_TEXT>44</NMB_TEXT>
<TEXT1>
<MASK>0x80</MASK>
<VALUE>0x00</VALUE>
<TEXT>Divide clock by 8 internally; [CKDIV8=0]</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x40</MASK>
<VALUE>0x00</VALUE>
<TEXT>Clock output on PORTD1; [CKOUT=0]</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x3F</MASK>
<VALUE>0x00</VALUE>
<TEXT>Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0000 SUT=00]</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x3F</MASK>
<VALUE>0x10</VALUE>
<TEXT>Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0000 SUT=01]</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x3F</MASK>
<VALUE>0x20</VALUE>
<TEXT>Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0000 SUT=10]</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x3F</MASK>
<VALUE>0x02</VALUE>
<TEXT>Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0010 SUT=00]</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x3F</MASK>
<VALUE>0x12</VALUE>
<TEXT>Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0010 SUT=01]</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x3F</MASK>
<VALUE>0x22</VALUE>
<TEXT>Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0010 SUT=10]; default value</TEXT>
</TEXT8>
<TEXT9>
<MASK>0x3F</MASK>
<VALUE>0x08</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1000 SUT=00] </TEXT>
</TEXT9>
<TEXT10>
<MASK>0x3F</MASK>
<VALUE>0x18</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1000 SUT=01] </TEXT>
</TEXT10>
<TEXT11>
<MASK>0x3F</MASK>
<VALUE>0x28</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1000 SUT=10] </TEXT>
</TEXT11>
<TEXT12>
<MASK>0x3F</MASK>
<VALUE>0x38</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1000 SUT=11] </TEXT>
</TEXT12>
<TEXT13>
<MASK>0x3F</MASK>
<VALUE>0x09</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1001 SUT=00] </TEXT>
</TEXT13>
<TEXT14>
<MASK>0x3F</MASK>
<VALUE>0x19</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1001 SUT=01] </TEXT>
</TEXT14>
<TEXT15>
<MASK>0x3F</MASK>
<VALUE>0x29</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1001 SUT=10] </TEXT>
</TEXT15>
<TEXT16>
<MASK>0x3F</MASK>
<VALUE>0x39</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1001 SUT=11] </TEXT>
</TEXT16>
<TEXT17>
<MASK>0x3F</MASK>
<VALUE>0x0A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1010 SUT=00] </TEXT>
</TEXT17>
<TEXT18>
<MASK>0x3F</MASK>
<VALUE>0x1A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1010 SUT=01] </TEXT>
</TEXT18>
<TEXT19>
<MASK>0x3F</MASK>
<VALUE>0x2A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1010 SUT=10] </TEXT>
</TEXT19>
<TEXT20>
<MASK>0x3F</MASK>
<VALUE>0x3A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1010 SUT=11] </TEXT>
</TEXT20>
<TEXT21>
<MASK>0x3F</MASK>
<VALUE>0x0B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1011 SUT=00] </TEXT>
</TEXT21>
<TEXT22>
<MASK>0x3F</MASK>
<VALUE>0x1B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1011 SUT=01] </TEXT>
</TEXT22>
<TEXT23>
<MASK>0x3F</MASK>
<VALUE>0x2B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1011 SUT=10] </TEXT>
</TEXT23>
<TEXT24>
<MASK>0x3F</MASK>
<VALUE>0x3B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1011 SUT=11] </TEXT>
</TEXT24>
<TEXT25>
<MASK>0x3F</MASK>
<VALUE>0x0C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1100 SUT=00] </TEXT>
</TEXT25>
<TEXT26>
<MASK>0x3F</MASK>
<VALUE>0x1C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1100 SUT=01] </TEXT>
</TEXT26>
<TEXT27>
<MASK>0x3F</MASK>
<VALUE>0x2C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1100 SUT=10] </TEXT>
</TEXT27>
<TEXT28>
<MASK>0x3F</MASK>
<VALUE>0x3C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1100 SUT=11] </TEXT>
</TEXT28>
<TEXT29>
<MASK>0x3F</MASK>
<VALUE>0x0D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1101 SUT=00] </TEXT>
</TEXT29>
<TEXT30>
<MASK>0x3F</MASK>
<VALUE>0x1D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1101 SUT=01] </TEXT>
</TEXT30>
<TEXT31>
<MASK>0x3F</MASK>
<VALUE>0x2D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1101 SUT=10] </TEXT>
</TEXT31>
<TEXT32>
<MASK>0x3F</MASK>
<VALUE>0x3D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1101 SUT=11] </TEXT>
</TEXT32>
<TEXT33>
<MASK>0x3F</MASK>
<VALUE>0x0E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1110 SUT=00] </TEXT>
</TEXT33>
<TEXT34>
<MASK>0x3F</MASK>
<VALUE>0x1E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1110 SUT=01] </TEXT>
</TEXT34>
<TEXT35>
<MASK>0x3F</MASK>
<VALUE>0x2E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1110 SUT=10] </TEXT>
</TEXT35>
<TEXT36>
<MASK>0x3F</MASK>
<VALUE>0x3E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1110 SUT=11] </TEXT>
</TEXT36>
<TEXT37>
<MASK>0x3F</MASK>
<VALUE>0x0F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1111 SUT=00] </TEXT>
</TEXT37>
<TEXT38>
<MASK>0x3F</MASK>
<VALUE>0x1F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1111 SUT=01] </TEXT>
</TEXT38>
<TEXT39>
<MASK>0x3F</MASK>
<VALUE>0x2F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1111 SUT=10] </TEXT>
</TEXT39>
<TEXT40>
<MASK>0x3F</MASK>
<VALUE>0x3F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1111 SUT=11] </TEXT>
</TEXT40>
<TEXT41>
<MASK>0x3F</MASK>
<VALUE>0x03</VALUE>
<TEXT>PLL clock; Frequency 16 MHz; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms; [CKSEL=0011 SUT=00]</TEXT>
</TEXT41>
<TEXT42>
<MASK>0x3F</MASK>
<VALUE>0x13</VALUE>
<TEXT>PLL clock; Frequency 16 MHz; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms; [CKSEL=0011 SUT=01]</TEXT>
</TEXT42>
<TEXT43>
<MASK>0x3F</MASK>
<VALUE>0x23</VALUE>
<TEXT>PLL clock; Frequency 16 MHz; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms; [CKSEL=0011 SUT=10]</TEXT>
</TEXT43>
<TEXT44>
<MASK>0x3F</MASK>
<VALUE>0x33</VALUE>
<TEXT>PLL clock; Frequency 16 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=0011 SUT=11]</TEXT>
</TEXT44>
</LOW>
<HIGH>
<NMB_FUSE_BITS>8</NMB_FUSE_BITS>
<FUSE7>
<NAME>RSTDISBL</NAME>
<TEXT>External Reset Diasble</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE7>
<FUSE6>
<NAME>DWEN</NAME>
<TEXT>debugWIRE Enable</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE6>
<FUSE5>
<NAME>SPIEN</NAME>
<TEXT>Enable Serial programming and Data Downloading</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE5>
<FUSE4>
<NAME>WDTON</NAME>
<TEXT>Watchdog timer always on</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE4>
<FUSE3>
<NAME>EESAVE</NAME>
<TEXT>EEPROM memory is preserved through chip erase</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE3>
<FUSE2>
<NAME>BOOTSZ1</NAME>
<TEXT>Select Boot Size</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE2>
<FUSE1>
<NAME>BOOTSZ0</NAME>
<TEXT>Select Boot Size</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE1>
<FUSE0>
<NAME>BOOTRST</NAME>
<TEXT>Select Reset Vector</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE0>
<NMB_TEXT>13</NMB_TEXT>
<TEXT1>
<MASK>0x80</MASK>
<VALUE>0x00</VALUE>
<TEXT>Reset Disabled (Enable PC6 as i/o pin); [RSTDISBL=0]</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x40</MASK>
<VALUE>0x00</VALUE>
<TEXT>Debug Wire enable; [DWEN=0]</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x20</MASK>
<VALUE>0x00</VALUE>
<TEXT>Serial program downloading (SPI) enabled; [SPIEN=0]</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x10</MASK>
<VALUE>0x00</VALUE>
<TEXT>Watch-dog Timer always on; [WDTON=0]</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x08</MASK>
<VALUE>0x00</VALUE>
<TEXT>Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x07</MASK>
<VALUE>0x07</VALUE>
<TEXT>Brown-out detection disabled; [BODLEVEL=111]</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x07</MASK>
<VALUE>0x06</VALUE>
<TEXT>Brown-out detection level at VCC=4.5 V; [BODLEVEL=110]</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x07</MASK>
<VALUE>0x05</VALUE>
<TEXT>Brown-out detection level at VCC=2.7 V; [BODLEVEL=101]</TEXT>
</TEXT8>
<TEXT9>
<MASK>0x07</MASK>
<VALUE>0x04</VALUE>
<TEXT>Brown-out detection level at VCC=4.3 V; [BODLEVEL=100]</TEXT>
</TEXT9>
<TEXT10>
<MASK>0x07</MASK>
<VALUE>0x03</VALUE>
<TEXT>Brown-out detection level at VCC=4.4 V; [BODLEVEL=011]</TEXT>
</TEXT10>
<TEXT11>
<MASK>0x07</MASK>
<VALUE>0x02</VALUE>
<TEXT>Brown-out detection level at VCC=4.2 V; [BODLEVEL=010]</TEXT>
</TEXT11>
<TEXT12>
<MASK>0x07</MASK>
<VALUE>0x01</VALUE>
<TEXT>Brown-out detection level at VCC=2.8 V; [BODLEVEL=001]</TEXT>
</TEXT12>
<TEXT13>
<MASK>0x07</MASK>
<VALUE>0x00</VALUE>
<TEXT>Brown-out detection level at VCC=2.6 V; [BODLEVEL=000] </TEXT>
</TEXT13>
</HIGH>
<EXTENDED>
<NMB_FUSE_BITS>4</NMB_FUSE_BITS>
<FUSE3>
<NAME>BODLEVEL2</NAME>
<TEXT>Brown out detector trigger level</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE3>
<FUSE2>
<NAME>BODLEVEL1</NAME>
<TEXT>Brown-out Detector trigger level</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE2>
<FUSE1>
<NAME>BODLEVEL0</NAME>
<TEXT>Brown-out Detector trigger level</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE1>
<FUSE0>
<NAME>TA0SEL</NAME>
<TEXT>(Reserved to factory tests)</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE0>
<NMB_TEXT>8</NMB_TEXT>
<TEXT1>
<MASK>0x10</MASK>
<VALUE>0x00</VALUE>
<TEXT>PSCOUT Reset Value; [PSCRV=1]</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x80</MASK>
<VALUE>0x00</VALUE>
<TEXT>PSC2 Reset Behavior; [PSC2RB=0]</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x20</MASK>
<VALUE>0x00</VALUE>
<TEXT>PSC0 Reset Behavior; [PSC0RB=0]</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x06</MASK>
<VALUE>0x06</VALUE>
<TEXT>Boot Flash section size=128 words Boot start address=$0F80; [BOOTSZ=11]</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x06</MASK>
<VALUE>0x04</VALUE>
<TEXT>Boot Flash section size=256 words Boot start address=$0F00; [BOOTSZ=10]</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x06</MASK>
<VALUE>0x02</VALUE>
<TEXT>Boot Flash section size=512 words Boot start address=$0E00; [BOOTSZ=01]</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x06</MASK>
<VALUE>0x00</VALUE>
<TEXT>Boot Flash section size=1024 words Boot start address=$0C00; [BOOTSZ=00] ; default value</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x01</MASK>
<VALUE>0x00</VALUE>
<TEXT>Boot Reset vector Enabled (default address=$0000); [BOOTRST=0]</TEXT>
</TEXT8>
</EXTENDED>
</FUSE>
<IO_MODULE><MODULE_LIST>[PORTB:PORTD:BOOT_LOAD:PSC0:PSC2:EUSART:ANALOG_COMPARATOR:DA_CONVERTER:CPU:PORTE:TIMER_COUNTER_0:TIMER_COUNTER_1:AD_CONVERTER:USART:SPI:WATCHDOG:EXTERNAL_INTERRUPT:EEPROM]</MODULE_LIST><PORTB>
<LIST>[PORTB:DDRB:PINB]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTB>
<NAME>PORTB</NAME>
<DESCRIPTION>Port B Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$05</IO_ADDR>
<MEM_ADDR>$25</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTB7</NAME>
<DESCRIPTION>Port B Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTB6</NAME>
<DESCRIPTION>Port B Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTB5</NAME>
<DESCRIPTION>Port B Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTB4</NAME>
<DESCRIPTION>Port B Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTB3</NAME>
<DESCRIPTION>Port B Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTB2</NAME>
<DESCRIPTION>Port B Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTB1</NAME>
<DESCRIPTION>Port B Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTB0</NAME>
<DESCRIPTION>Port B Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTB>
<DDRB>
<NAME>DDRB</NAME>
<DESCRIPTION>Port B Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$04</IO_ADDR>
<MEM_ADDR>$24</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDB7</NAME>
<DESCRIPTION>Port B Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDB6</NAME>
<DESCRIPTION>Port B Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDB5</NAME>
<DESCRIPTION>Port B Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDB4</NAME>
<DESCRIPTION>Port B Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDB3</NAME>
<DESCRIPTION>Port B Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDB2</NAME>
<DESCRIPTION>Port B Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDB1</NAME>
<DESCRIPTION>Port B Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDB0</NAME>
<DESCRIPTION>Port B Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRB>
<PINB>
<NAME>PINB</NAME>
<DESCRIPTION>Port B Input Pins</DESCRIPTION>
<TEXT>The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$03</IO_ADDR>
<MEM_ADDR>$23</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINB7</NAME>
<DESCRIPTION>Port B Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINB6</NAME>
<DESCRIPTION>Port B Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINB5</NAME>
<DESCRIPTION>Port B Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINB4</NAME>
<DESCRIPTION>Port B Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINB3</NAME>
<DESCRIPTION>Port B Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINB2</NAME>
<DESCRIPTION>Port B Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINB1</NAME>
<DESCRIPTION>Port B Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINB0</NAME>
<DESCRIPTION>Port B Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINB>
</PORTB>
<PORTD>
<LIST>[PORTD:DDRD:PIND]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTD>
<NAME>PORTD</NAME>
<DESCRIPTION>Port D Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0B</IO_ADDR>
<MEM_ADDR>$2B</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTD7</NAME>
<DESCRIPTION>Port D Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTD6</NAME>
<DESCRIPTION>Port D Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTD5</NAME>
<DESCRIPTION>Port D Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTD4</NAME>
<DESCRIPTION>Port D Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTD3</NAME>
<DESCRIPTION>Port D Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTD2</NAME>
<DESCRIPTION>Port D Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTD1</NAME>
<DESCRIPTION>Port D Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTD0</NAME>
<DESCRIPTION>Port D Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTD>
<DDRD>
<NAME>DDRD</NAME>
<DESCRIPTION>Port D Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0A</IO_ADDR>
<MEM_ADDR>$2A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDD7</NAME>
<DESCRIPTION>Port D Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDD6</NAME>
<DESCRIPTION>Port D Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDD5</NAME>
<DESCRIPTION>Port D Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDD4</NAME>
<DESCRIPTION>Port D Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDD3</NAME>
<DESCRIPTION>Port D Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDD2</NAME>
<DESCRIPTION>Port D Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDD1</NAME>
<DESCRIPTION>Port D Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDD0</NAME>
<DESCRIPTION>Port D Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRD>
<PIND>
<NAME>PIND</NAME>
<DESCRIPTION>Port D Input Pins</DESCRIPTION>
<TEXT>The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$09</IO_ADDR>
<MEM_ADDR>$29</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PIND7</NAME>
<DESCRIPTION>Port D Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PIND6</NAME>
<DESCRIPTION>Port D Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PIND5</NAME>
<DESCRIPTION>Port D Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PIND4</NAME>
<DESCRIPTION>Port D Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PIND3</NAME>
<DESCRIPTION>Port D Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PIND2</NAME>
<DESCRIPTION>Port D Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PIND1</NAME>
<DESCRIPTION>Port D Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PIND0</NAME>
<DESCRIPTION>Port D Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PIND>
</PORTD>
<BOOT_LOAD>
<LIST>[SPMCSR]</LIST>
<LINK/>
<RULES/>
<ICON>io_cpu.bmp</ICON>
<ID>AVRSimIOSPM.SimIOSPM</ID>
<TEXT>The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppor</TEXT>
<SPMCSR>
<NAME>SPMCSR</NAME>
<ALIAS>SPMCR</ALIAS>
<DESCRIPTION>Store Program Memory Control Register</DESCRIPTION>
<TEXT>The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.</TEXT>
<IO_ADDR>$37</IO_ADDR>
<MEM_ADDR>$57</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SPMIE</NAME>
<DESCRIPTION>SPM Interrupt Enable</DESCRIPTION>
<TEXT>When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>RWWSB</NAME>
<ALIAS>ASB</ALIAS>
<DESCRIPTION>Read While Write Section Busy</DESCRIPTION>
<TEXT>When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT4>
<NAME>RWWSRE</NAME>
<ALIAS>ASRE</ALIAS>
<DESCRIPTION>Read While Write section read enable</DESCRIPTION>
<TEXT>When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>BLBSET</NAME>
<DESCRIPTION>Boot Lock Bit Set</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 235 for details</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PGWRT</NAME>
<DESCRIPTION>Page Write</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PGERS</NAME>
<DESCRIPTION>Page Erase</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPMEN</NAME>
<DESCRIPTION>Store Program Memory Enable</DESCRIPTION>
<TEXT>This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPMCSR>
</BOOT_LOAD>
<PSC0>
<LIST>[PICR0H:PICR0L:PFRC0B:PFRC0A:PCTL0:PCNF0:OCR0RBH:OCR0RBL:OCR0SBH:OCR0SBL:OCR0RAH:OCR0RAL:OCR0SAH:OCR0SAL:PSOC0:PIM0:PIFR0]</LIST>
<LINK/>
<ICON>io_com.bmp</ICON>
<ID/>
<TEXT>Power Stage Controller</TEXT>
<PICR0H>
<NAME>PICR0H</NAME>
<DESCRIPTION>PSC 0 Input Capture Register High</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xDF</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>PICR0_11</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PICR0_10</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PICR0_9</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PICR0_8</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PICR0H>
<PICR0L>
<NAME>PICR0L</NAME>
<DESCRIPTION>PSC 0 Input Capture Register Low</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xDE</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PICR0_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PICR0_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PICR0_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PICR0_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PICR0_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PICR0_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PICR0_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PICR0_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PICR0L>
<PFRC0B>
<NAME>PFRC0B</NAME>
<DESCRIPTION>PSC 0 Input B Control</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xDD</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>PCAE0B</NAME>
<DESCRIPTION>PSC 0 Capture Enable Input Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PISEL0B</NAME>
<DESCRIPTION>PSC 0 Input Select for Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PELEV0B</NAME>
<DESCRIPTION>PSC 0 Edge Level Selector on Input Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PFLTE0B</NAME>
<DESCRIPTION>PSC 0 Filter Enable on Input Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PRFM0B3</NAME>
<DESCRIPTION>PSC 0 Retrigger and Fault Mode for Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PRFM0B2</NAME>
<DESCRIPTION>PSC 0 Retrigger and Fault Mode for Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PRFM0B1</NAME>
<DESCRIPTION>PSC 0 Retrigger and Fault Mode for Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PRFM0B0</NAME>
<DESCRIPTION>PSC 0 Retrigger and Fault Mode for Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PFRC0B>
<PFRC0A>
<NAME>PFRC0A</NAME>
<DESCRIPTION>PSC 0 Input A Control</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xDC</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>PCAE0A</NAME>
<DESCRIPTION>PSC 0 Capture Enable Input Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PISEL0A</NAME>
<DESCRIPTION>PSC 0 Input Select for Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PELEV0A</NAME>
<DESCRIPTION>PSC 0 Edge Level Selector on Input Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PFLTE0A</NAME>
<DESCRIPTION>PSC 0 Filter Enable on Input Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PRFM0A3</NAME>
<DESCRIPTION>PSC 0 Retrigger and Fault Mode for Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PRFM0A2</NAME>
<DESCRIPTION>PSC 0 Retrigger and Fault Mode for Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PRFM0A1</NAME>
<DESCRIPTION>PSC 0 Retrigger and Fault Mode for Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PRFM0A0</NAME>
<DESCRIPTION>PSC 0 Retrigger and Fault Mode for Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PFRC0A>
<PCTL0>
<NAME>PCTL0</NAME>
<DESCRIPTION>PSC 0 Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xDB</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>PPRE01</NAME>
<DESCRIPTION>PSC 0 Prescaler Select 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PPRE00</NAME>
<DESCRIPTION>PSC 0 Prescaler Select 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PBFM0</NAME>
<DESCRIPTION>PSC 0 Balance Flank Width Modulation</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PAOC0B</NAME>
<DESCRIPTION>PSC 0 Asynchronous Output Control B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PAOC0A</NAME>
<DESCRIPTION>PSC 0 Asynchronous Output Control A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PARUN0</NAME>
<DESCRIPTION>PSC0 Auto Run</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PCCYC0</NAME>
<DESCRIPTION>PSC0 Complete Cycle</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PRUN0</NAME>
<DESCRIPTION>PSC 0 Run</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PCTL0>
<PCNF0>
<NAME>PCNF0</NAME>
<DESCRIPTION>PSC 0 Configuration Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xDA</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>PFIFTY0</NAME>
<DESCRIPTION>PSC 0 Fifty</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PALOCK0</NAME>
<DESCRIPTION>PSC 0 Autolock</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PLOCK0</NAME>
<DESCRIPTION>PSC 0 Lock</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PMODE01</NAME>
<DESCRIPTION>PSC 0 Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PMODE00</NAME>
<DESCRIPTION>PSC 0 Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>POP0</NAME>
<DESCRIPTION>PSC 0 Output Polarity</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PCLKSEL0</NAME>
<DESCRIPTION>PSC 0 Input Clock Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
</PCNF0>
<OCR0RBH>
<NAME>OCR0RBH</NAME>
<DESCRIPTION>Output Compare RB Register High</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD9</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR0RB_05</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR0RB_04</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR0RB_03</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR0RB_02</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR0RB_01</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0RB_00</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0RB_9</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0RB_8</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0RBH>
<OCR0RBL>
<NAME>OCR0RBL</NAME>
<DESCRIPTION>Output Compare RB Register Low</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD8</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR0RB_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR0RB_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR0RB_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR0RB_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR0RB_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0RB_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0RB_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0RB_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0RBL>
<OCR0SBH>
<NAME>OCR0SBH</NAME>
<DESCRIPTION>Output Compare SB Register High</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD7</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>OCR0SB_01</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0SB_00</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0SB_9</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0SB_8</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0SBH>
<OCR0SBL>
<NAME>OCR0SBL</NAME>
<DESCRIPTION>Output Compare SB Register Low</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD6</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR0SB_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR0SB_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR0SB_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR0SB_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR0SB_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0SB_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0SB_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0SB_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0SBL>
<OCR0RAH>
<NAME>OCR0RAH</NAME>
<DESCRIPTION>Output Compare RA Register High</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD5</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>OCR0RA_01</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0RA_00</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0RA_9</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0RA_8</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0RAH>
<OCR0RAL>
<NAME>OCR0RAL</NAME>
<DESCRIPTION>Output Compare RA Register Low</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD4</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR0RA_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR0RA_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR0RA_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR0RA_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR0RA_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0RA_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0RA_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0RA_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0RAL>
<OCR0SAH>
<NAME>OCR0SAH</NAME>
<DESCRIPTION>Output Compare SA Register High</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD3</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>OCR0SA_01</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0SA_00</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0SA_9</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0SA_8</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0SAH>
<OCR0SAL>
<NAME>OCR0SAL</NAME>
<DESCRIPTION>Output Compare SA Register Low</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD2</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR0SA_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR0SA_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR0SA_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR0SA_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR0SA_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0SA_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0SA_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0SA_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0SAL>
<PSOC0>
<NAME>PSOC0</NAME>
<DESCRIPTION>PSC0 Synchro and Output Configuration</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD0</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>PSYNC01</NAME>
<DESCRIPTION>Synchronization Out for ADC Selection</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PSYNC00</NAME>
<DESCRIPTION>Synchronization Out for ADC Selection</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT2>
<NAME>POEN0B</NAME>
<DESCRIPTION>PSCOUT01 Output Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT0>
<NAME>POEN0A</NAME>
<DESCRIPTION>PSCOUT00 Output Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PSOC0>
<PIM0>
<NAME>PIM0</NAME>
<DESCRIPTION>PSC0 Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A1</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>PSEIE0</NAME>
<DESCRIPTION>PSC 0 Synchro Error Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PEVE0B</NAME>
<DESCRIPTION>External Event B Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PEVE0A</NAME>
<DESCRIPTION>External Event A Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT0>
<NAME>PEOPE0</NAME>
<DESCRIPTION>End of Cycle Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PIM0>
<PIFR0>
<NAME>PIFR0</NAME>
<DESCRIPTION>PSC0 Interrupt Flag Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A0</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>PSEI0</NAME>
<DESCRIPTION>PSC 0 Synchro Error Interrupt</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PEV0B</NAME>
<DESCRIPTION>External Event B Interrupt</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PEV0A</NAME>
<DESCRIPTION>External Event A Interrupt</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PRN01</NAME>
<DESCRIPTION>Ramp Number</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PRN00</NAME>
<DESCRIPTION>Ramp Number</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PEOP0</NAME>
<DESCRIPTION>End of PSC0 Interrupt</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PIFR0>
</PSC0>
<PSC2>
<LIST>[PICR2H:PICR2L:PFRC2B:PFRC2A:PCTL2:PCNF2:OCR2RBH:OCR2RBL:OCR2SBH:OCR2SBL:OCR2RAH:OCR2RAL:OCR2SAH:OCR2SAL:POM2:PSOC2:PIM2:PIFR2]</LIST>
<LINK/>
<ICON>io_com.bmp</ICON>
<ID/>
<TEXT>Power Stage Controller</TEXT>
<PICR2H>
<NAME>PICR2H</NAME>
<DESCRIPTION>PSC 2 Input Capture Register High</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xFF</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>PICR2_11</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PICR2_10</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PICR2_9</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PICR2_8</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PICR2H>
<PICR2L>
<NAME>PICR2L</NAME>
<DESCRIPTION>PSC 2 Input Capture Register Low</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xFE</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PICR2_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PICR2_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PICR2_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PICR2_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PICR2_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PICR2_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PICR2_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PICR2_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PICR2L>
<PFRC2B>
<NAME>PFRC2B</NAME>
<DESCRIPTION>PSC 2 Input B Control</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xFD</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>PCAE2B</NAME>
<DESCRIPTION>PSC 2 Capture Enable Input Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PISEL2B</NAME>
<DESCRIPTION>PSC 2 Input Select for Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PELEV2B</NAME>
<DESCRIPTION>PSC 2 Edge Level Selector on Input Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PFLTE2B</NAME>
<DESCRIPTION>PSC 2 Filter Enable on Input Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PRFM2B3</NAME>
<DESCRIPTION>PSC 2 Retrigger and Fault Mode for Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PRFM2B2</NAME>
<DESCRIPTION>PSC 2 Retrigger and Fault Mode for Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PRFM2B1</NAME>
<DESCRIPTION>PSC 2 Retrigger and Fault Mode for Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PRFM2B0</NAME>
<DESCRIPTION>PSC 2 Retrigger and Fault Mode for Part B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PFRC2B>
<PFRC2A>
<NAME>PFRC2A</NAME>
<DESCRIPTION>PSC 2 Input B Control</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xFC</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>PCAE2A</NAME>
<DESCRIPTION>PSC 2 Capture Enable Input Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PISEL2A</NAME>
<DESCRIPTION>PSC 2 Input Select for Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PELEV2A</NAME>
<DESCRIPTION>PSC 2 Edge Level Selector on Input Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PFLTE2A</NAME>
<DESCRIPTION>PSC 2 Filter Enable on Input Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PRFM2A3</NAME>
<DESCRIPTION>PSC 2 Retrigger and Fault Mode for Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PRFM2A2</NAME>
<DESCRIPTION>PSC 2 Retrigger and Fault Mode for Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PRFM2A1</NAME>
<DESCRIPTION>PSC 2 Retrigger and Fault Mode for Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PRFM2A0</NAME>
<DESCRIPTION>PSC 2 Retrigger and Fault Mode for Part A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PFRC2A>
<PCTL2>
<NAME>PCTL2</NAME>
<DESCRIPTION>PSC 2 Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xFB</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>PPRE21</NAME>
<DESCRIPTION>PSC 2 Prescaler Select 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PPRE20</NAME>
<DESCRIPTION>PSC 2 Prescaler Select 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PBFM2</NAME>
<DESCRIPTION>Balance Flank Width Modulation</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PAOC2B</NAME>
<DESCRIPTION>PSC 2 Asynchronous Output Control B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PAOC2A</NAME>
<DESCRIPTION>PSC 2 Asynchronous Output Control A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PARUN2</NAME>
<DESCRIPTION>PSC2 Auto Run</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PCCYC2</NAME>
<DESCRIPTION>PSC2 Complete Cycle</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PRUN2</NAME>
<DESCRIPTION>PSC 2 Run</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PCTL2>
<PCNF2>
<NAME>PCNF2</NAME>
<DESCRIPTION>PSC 2 Configuration Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xFA</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>PFIFTY2</NAME>
<DESCRIPTION>PSC 2 Fifty</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PALOCK2</NAME>
<DESCRIPTION>PSC 2 Autolock</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PLOCK2</NAME>
<DESCRIPTION>PSC 2 Lock</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PMODE21</NAME>
<DESCRIPTION>PSC 2 Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PMODE20</NAME>
<DESCRIPTION>PSC 2 Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>POP2</NAME>
<DESCRIPTION>PSC 2 Output Polarity</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PCLKSEL2</NAME>
<DESCRIPTION>PSC 2 Input Clock Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>POME2</NAME>
<DESCRIPTION>PSC 2 Output Matrix Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PCNF2>
<OCR2RBH>
<NAME>OCR2RBH</NAME>
<DESCRIPTION>Output Compare RB Register High</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF9</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR2RB_15</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR2RB_14</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR2RB_13</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR2RB_12</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR2RB_11</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR2RB_10</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR2RB_9</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR2RB_8</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR2RBH>
<OCR2RBL>
<NAME>OCR2RBL</NAME>
<DESCRIPTION>Output Compare RB Register Low</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF8</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR2RB_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR2RB_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR2RB_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR2RB_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR2RB_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR2RB_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR2RB_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR2RB_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR2RBL>
<OCR2SBH>
<NAME>OCR2SBH</NAME>
<DESCRIPTION>Output Compare SB Register High</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF7</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>OCR2SB_11</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR2SB_10</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR2SB_9</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR2SB_8</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR2SBH>
<OCR2SBL>
<NAME>OCR2SBL</NAME>
<DESCRIPTION>Output Compare SB Register Low</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF6</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR2SB_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR2SB_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR2SB_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR2SB_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR2SB_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR2SB_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR2SB_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR2SB_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR2SBL>
<OCR2RAH>
<NAME>OCR2RAH</NAME>
<DESCRIPTION>Output Compare RA Register High</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF5</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>OCR2RA_11</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR2RA_10</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR2RA_9</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR2RA_8</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR2RAH>
<OCR2RAL>
<NAME>OCR2RAL</NAME>
<DESCRIPTION>Output Compare RA Register Low</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF4</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR2RA_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR2RA_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR2RA_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR2RA_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR2RA_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR2RA_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR2RA_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR2RA_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR2RAL>
<OCR2SAH>
<NAME>OCR2SAH</NAME>
<DESCRIPTION>Output Compare SA Register High</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF3</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>OCR2SA_11</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR2SA_10</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR2SA_9</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR2SA_8</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR2SAH>
<OCR2SAL>
<NAME>OCR2SAL</NAME>
<DESCRIPTION>Output Compare SA Register Low</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF2</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR2SA_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR2SA_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR2SA_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR2SA_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR2SA_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR2SA_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR2SA_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR2SA_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR2SAL>
<POM2>
<NAME>POM2</NAME>
<DESCRIPTION>PSC 2 Output Matrix</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF1</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>POMV2B3</NAME>
<DESCRIPTION>Output Matrix Output B Ramp 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>POMV2B2</NAME>
<DESCRIPTION>Output Matrix Output B Ramp 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>POMV2B1</NAME>
<DESCRIPTION>Output Matrix Output B Ramp 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>POMV2B0</NAME>
<DESCRIPTION>Output Matrix Output B Ramp 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>POMV2A3</NAME>
<DESCRIPTION>Output Matrix Output A Ramp 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>POMV2A2</NAME>
<DESCRIPTION>Output Matrix Output A Ramp 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>POMV2A1</NAME>
<DESCRIPTION>Output Matrix Output A Ramp 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>POMV2A0</NAME>
<DESCRIPTION>Output Matrix Output A Ramp 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</POM2>
<PSOC2>
<NAME>PSOC2</NAME>
<DESCRIPTION>PSC2 Synchro and Output Configuration</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF0</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>POS23</NAME>
<DESCRIPTION>PSC 2 Output 23 Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>POS22</NAME>
<DESCRIPTION>PSC 2 Output 22 Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PSYNC2_1</NAME>
<DESCRIPTION>Synchronization Out for ADC Selection</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PSYNC2_0</NAME>
<DESCRIPTION>Synchronization Out for ADC Selection</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>POEN2D</NAME>
<DESCRIPTION>PSCOUT23 Output Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>POEN2B</NAME>
<DESCRIPTION>PSCOUT21 Output Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>POEN2C</NAME>
<DESCRIPTION>PSCOUT22 Output Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>POEN2A</NAME>
<DESCRIPTION>PSCOUT20 Output Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PSOC2>
<PIM2>
<NAME>PIM2</NAME>
<DESCRIPTION>PSC2 Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A5</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>PSEIE2</NAME>
<DESCRIPTION>PSC 2 Synchro Error Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PEVE2B</NAME>
<DESCRIPTION>External Event B Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PEVE2A</NAME>
<DESCRIPTION>External Event A Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT0>
<NAME>PEOPE2</NAME>
<DESCRIPTION>End of Cycle Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PIM2>
<PIFR2>
<NAME>PIFR2</NAME>
<DESCRIPTION>PSC2 Interrupt Flag Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A4</MEM_ADDR>
<ICON>register.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>PSEI2</NAME>
<DESCRIPTION>PSC 2 Synchro Error Interrupt</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PEV2B</NAME>
<DESCRIPTION>External Event B Interrupt</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PEV2A</NAME>
<DESCRIPTION>External Event A Interrupt</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PRN21</NAME>
<DESCRIPTION>Ramp Number</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PRN20</NAME>
<DESCRIPTION>Ramp Number</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PEOP2</NAME>
<DESCRIPTION>End of PSC2 Interrupt</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PIFR2>
</PSC2>
<EUSART>
<LIST>[EUDR:EUCSRA:EUCSRB:EUCSRC:MUBRRH:MUBRRL]</LIST>
<LINK>[MUBRRH:MUBRRL]</LINK>
<ICON>io_com.bmp</ICON>
<ID/>
<TEXT/>
<EUDR>
<NAME>EUDR</NAME>
<DESCRIPTION>EUSART I/O Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xCE</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>EUDR7</NAME>
<DESCRIPTION>EUSART I/O Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>EUDR6</NAME>
<DESCRIPTION>EUSART I/O Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>EUDR5</NAME>
<DESCRIPTION>EUSART I/O Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EUDR4</NAME>
<DESCRIPTION>EUSART I/O Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EUDR3</NAME>
<DESCRIPTION>EUSART I/O Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EUDR2</NAME>
<DESCRIPTION>EUSART I/O Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EUDR1</NAME>
<DESCRIPTION>EUSART I/O Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EUDR0</NAME>
<DESCRIPTION>EUSART I/O Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EUDR>
<EUCSRA>
<NAME>EUCSRA</NAME>
<DESCRIPTION>EUSART Control and Status Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC8</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>UTxS3</NAME>
<DESCRIPTION>EUSART Control and Status Register A Bit 7</DESCRIPTION>
<TEXT>.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UTxS2</NAME>
<DESCRIPTION>EUSART Control and Status Register A Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UTxS1</NAME>
<DESCRIPTION>EUSART Control and Status Register A Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UTxS0</NAME>
<DESCRIPTION>EUSART Control and Status Register A Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT4>
<BIT3>
<NAME>URxS3</NAME>
<DESCRIPTION>EUSART Control and Status Register A Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>URxS2</NAME>
<DESCRIPTION>EUSART Control and Status Register A Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>URxS1</NAME>
<DESCRIPTION>EUSART Control and Status Register A Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT1>
<BIT0>
<NAME>URxS0</NAME>
<DESCRIPTION>EUSART Control and Status Register A Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT0>
</EUCSRA>
<EUCSRB>
<NAME>EUCSRB</NAME>
<DESCRIPTION>EUSART Control Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC9</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT4>
<NAME>EUSART</NAME>
<DESCRIPTION>EUSART Enable Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EUSBS</NAME>
<DESCRIPTION>EUSBS Enable Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT1>
<NAME>EMCH</NAME>
<DESCRIPTION>Manchester Mode Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>BODR</NAME>
<DESCRIPTION>Order Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EUCSRB>
<EUCSRC>
<NAME>EUCSRC</NAME>
<DESCRIPTION>EUSART Status Register C</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xCA</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>FEM</NAME>
<DESCRIPTION>Frame Error Manchester Bit</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>F1617</NAME>
<DESCRIPTION>F1617 Bit</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>STP1</NAME>
<DESCRIPTION>Stop Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>STP0</NAME>
<DESCRIPTION>Stop Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EUCSRC>
<MUBRRH>
<NAME>MUBRRH</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register High Byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xCD</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>MUBRR15</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 15</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>MUBRR14</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 14</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>MUBRR13</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 13</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>MUBRR12</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 12</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>MUBRR11</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>MUBRR10</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>MUBRR9</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>MUBRR8</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MUBRRH>
<MUBRRL>
<NAME>MUBRRL</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Low Byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xCC</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>MUBRR7</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>MUBRR6</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>MUBRR5</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>MUBRR4</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>MUBRR3</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>MUBRR2</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>MUBRR1</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>MUBRR0</NAME>
<DESCRIPTION>Manchester Receiver Baud Rate Register Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MUBRRL>
</EUSART>
<ANALOG_COMPARATOR>
<LIST>[AC0CON:AC1CON:AC2CON]</LIST>
<LINK/>
<ICON>io_analo.bmp</ICON>
<ID>AlgComp_14</ID>
<TEXT/>
<AC0CON>
<NAME>AC0CON</NAME>
<DESCRIPTION>Analog Comparator 0 Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AD</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>AC0EN</NAME>
<DESCRIPTION>Analog Comparator 0 Enable Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>AC0IE</NAME>
<DESCRIPTION>Analog Comparator 0 Interrupt Enable Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>AC0IS1</NAME>
<DESCRIPTION>Analog Comparator 0 Interrupt Select Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>AC0IS0</NAME>
<DESCRIPTION>Analog Comparator 0 Interrupt Select Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT2>
<NAME>AC0M2</NAME>
<DESCRIPTION>Analog Comparator 0 Multiplexer Register</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>AC0M1</NAME>
<DESCRIPTION>Analog Comparator 0 Multiplexer Regsiter</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>AC0M0</NAME>
<DESCRIPTION>Analog Comparator 0 Multiplexer Register</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</AC0CON>
<AC1CON>
<NAME>AC1CON</NAME>
<DESCRIPTION>Analog Comparator 1 Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AE</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>AC1EN</NAME>
<DESCRIPTION>Analog Comparator 1 Enable Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>AC1IE</NAME>
<DESCRIPTION>Analog Comparator 1 Interrupt Enable Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>AC1IS1</NAME>
<DESCRIPTION>Analog Comparator 1 Interrupt Select Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>AC1IS0</NAME>
<DESCRIPTION>Analog Comparator 1 Interrupt Select Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>AC1ICE</NAME>
<DESCRIPTION>Analog Comparator 1 Interrupt Capture Enable Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>AC1M2</NAME>
<DESCRIPTION>Analog Comparator 1 Multiplexer Register</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>AC1M1</NAME>
<DESCRIPTION>Analog Comparator 1 Multiplexer Regsiter</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>AC1M0</NAME>
<DESCRIPTION>Analog Comparator 1 Multiplexer Register</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</AC1CON>
<AC2CON>
<NAME>AC2CON</NAME>
<DESCRIPTION>Analog Comparator 2 Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AF</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>AC2EN</NAME>
<DESCRIPTION>Analog Comparator 2 Enable Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>AC2IE</NAME>
<DESCRIPTION>Analog Comparator 2 Interrupt Enable Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>AC2IS1</NAME>
<DESCRIPTION>Analog Comparator 2 Interrupt Select Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>AC2IS0</NAME>
<DESCRIPTION>Analog Comparator 2 Interrupt Select Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT2>
<NAME>AC2M2</NAME>
<DESCRIPTION>Analog Comparator 2 Multiplexer Register</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>AC2M1</NAME>
<DESCRIPTION>Analog Comparator 2 Multiplexer Regsiter</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>AC2M0</NAME>
<DESCRIPTION>Analog Comparator 2 Multiplexer Register</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</AC2CON>
<ACSR>
<NAME>ACSR</NAME>
<DESCRIPTION>Analog Comparator Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR/>
<MEM_ADDR/>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ACCKDIV</NAME>
<DESCRIPTION>Analog Comparator Clock Divider</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>AC2IF</NAME>
<DESCRIPTION>Analog Comparator 2 Interrupt Flag Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>AC1IF</NAME>
<DESCRIPTION>Analog Comparator 1 Interrupt Flag Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>AC0IF</NAME>
<DESCRIPTION>Analog Comparator 0 Interrupt Flag Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT2>
<NAME>AC2O</NAME>
<DESCRIPTION>Analog Comparator 2 Output Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>AC1O</NAME>
<DESCRIPTION>Analog Comparator 1 Output Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>AC0O</NAME>
<DESCRIPTION>Analog Comparator 0 Output Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ACSR>
</ANALOG_COMPARATOR>
<DA_CONVERTER>
<LIST>[DACH:DACL:DACON]</LIST>
<LINK/>
<RULES>((IF DACON.DALA = 0) LINK [DACH(1:0):DACL(7:0)]); (IF DACON.DALA = 1) LINK [DACH(7:0):DACL(7:6)]);</RULES>
<ICON>io_analo.bmp</ICON>
<ID/>
<TEXT>Digital to Analog Converter</TEXT>
<DACH>
<NAME>DACH</NAME>
<DESCRIPTION>DAC Data Register High Byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AC</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>DACH7</NAME>
<DESCRIPTION>DAC Data Register High Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DACH6</NAME>
<DESCRIPTION>DAC Data Register High Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DACH5</NAME>
<DESCRIPTION>DAC Data Register High Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DACH4</NAME>
<DESCRIPTION>DAC Data Register High Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DACH3</NAME>
<DESCRIPTION>DAC Data Register High Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DACH2</NAME>
<DESCRIPTION>DAC Data Register High Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DACH1</NAME>
<DESCRIPTION>DAC Data Register High Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DACH0</NAME>
<DESCRIPTION>DAC Data Register High Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DACH>
<DACL>
<NAME>DACL</NAME>
<DESCRIPTION>DAC Data Register Low Byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AB</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>DACL7</NAME>
<DESCRIPTION>DAC Data Register Low Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DACL6</NAME>
<DESCRIPTION>DAC Data Register Low Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DACL5</NAME>
<DESCRIPTION>DAC Data Register Low Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DACL4</NAME>
<DESCRIPTION>DAC Data Register Low Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DACL3</NAME>
<DESCRIPTION>DAC Data Register Low Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DACL2</NAME>
<DESCRIPTION>DAC Data Register Low Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DACL1</NAME>
<DESCRIPTION>DAC Data Register Low Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DACL0</NAME>
<DESCRIPTION>DAC Data Register Low Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DACL>
<DACON>
<NAME>DACON</NAME>
<DESCRIPTION>DAC Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AA</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DAATE</NAME>
<DESCRIPTION>DAC Auto Trigger Enable Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DATS2</NAME>
<DESCRIPTION>DAC Trigger Selection Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DATS1</NAME>
<DESCRIPTION>DAC Trigger Selection Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DATS0</NAME>
<DESCRIPTION>DAC Trigger Selection Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT2>
<NAME>DALA</NAME>
<DESCRIPTION>DAC Left Adjust</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DAOE</NAME>
<DESCRIPTION>DAC Output Enable Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DAEN</NAME>
<DESCRIPTION>DAC Enable Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DACON>
</DA_CONVERTER>
<CPU>
<LIST>[SREG:SPH:SPL:MCUCR:MCUSR:OSCCAL:CLKPR:SMCR:GPIOR3:GPIOR2:GPIOR1:GPIOR0:PLLCSR]</LIST>
<LINK>[SPH:SPL]</LINK>
<ICON>io_cpu.bmp</ICON>
<ID/>
<TEXT/>
<SREG>
<NAME>SREG</NAME>
<DESCRIPTION>Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3F</IO_ADDR>
<MEM_ADDR>$5F</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>I</NAME>
<DESCRIPTION>Global Interrupt Enable</DESCRIPTION>
<TEXT>The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>T</NAME>
<DESCRIPTION>Bit Copy Storage</DESCRIPTION>
<TEXT>The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>H</NAME>
<DESCRIPTION>Half Carry Flag</DESCRIPTION>
<TEXT>The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>S</NAME>
<DECRIPTION>Sign Bit</DECRIPTION>
<TEXT>The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>V</NAME>
<DESCRIPTION>Two's Complement Overflow Flag</DESCRIPTION>
<TEXT>The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>N</NAME>
<DESCRIPTION>Negative Flag</DESCRIPTION>
<TEXT>The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>Z</NAME>
<DESCRIPTION>Zero Flag</DESCRIPTION>
<TEXT>The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>C</NAME>
<DESCRIPTION>Carry Flag</DESCRIPTION>
<TEXT>The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SREG>
<SPH>
<NAME>SPH</NAME>
<DESCRIPTION>Stack Pointer High</DESCRIPTION>
<TEXT>The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R</TEXT>
<IO_ADDR>$3E</IO_ADDR>
<MEM_ADDR>$5E</MEM_ADDR>
<ICON>io_sph.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SP15</NAME>
<DESCRIPTION>Stack pointer bit 15</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SP14</NAME>
<DESCRIPTION>Stack pointer bit 14</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SP13</NAME>
<DESCRIPTION>Stack pointer bit 13</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SP12</NAME>
<DECRIPTION>Stack pointer bit 12</DECRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SP11</NAME>
<DESCRIPTION>Stack pointer bit 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SP10</NAME>
<DESCRIPTION>Stack pointer bit 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SP9</NAME>
<DESCRIPTION>Stack pointer bit 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SP8</NAME>
<DESCRIPTION>Stack pointer bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPH>
<SPL>
<NAME>SPL</NAME>
<DESCRIPTION>Stack Pointer Low</DESCRIPTION>
<TEXT>The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt </TEXT>
<IO_ADDR>$3D</IO_ADDR>
<MEM_ADDR>$5D</MEM_ADDR>
<ICON>io_sph.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SP7</NAME>
<DESCRIPTION>Stack pointer bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SP6</NAME>
<DESCRIPTION>Stack pointer bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SP5</NAME>
<DESCRIPTION>Stack pointer bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SP4</NAME>
<DECRIPTION>Stack pointer bit 4</DECRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SP3</NAME>
<DESCRIPTION>Stack pointer bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SP2</NAME>
<DESCRIPTION>Stack pointer bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SP1</NAME>
<DESCRIPTION>Stack pointer bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SP0</NAME>
<DESCRIPTION>Stack pointer bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPL>
<MCUCR>
<NAME>MCUCR</NAME>
<DESCRIPTION>MCU Control Register</DESCRIPTION>
<TEXT>The MCU Control Register contains control bits for general MCU functions.</TEXT>
<IO_ADDR>$35</IO_ADDR>
<MEM_ADDR>$55</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SPIPS</NAME>
<DESCRIPTION>SPI Pin Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT4>
<NAME>PUD</NAME>
<DESCRIPTION>Pull-up disable</DESCRIPTION>
<TEXT>When this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01). </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT1>
<NAME>IVSEL</NAME>
<DESCRIPTION>Interrupt Vector Select</DESCRIPTION>
<TEXT>When the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>IVCE</NAME>
<DESCRIPTION>Interrupt Vector Change Enable</DESCRIPTION>
<TEXT>The IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUCR>
<MCUSR>
<NAME>MCUSR</NAME>
<DESCRIPTION>MCU Status Register</DESCRIPTION>
<TEXT>The MCU Status Register provides information on which reset source caused an MCU reset.</TEXT>
<IO_ADDR>$34</IO_ADDR>
<MEM_ADDR>$54</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>WDRF</NAME>
<DESCRIPTION>Watchdog Reset Flag</DESCRIPTION>
<TEXT>This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>BORF</NAME>
<DESCRIPTION>Brown-out Reset Flag</DESCRIPTION>
<TEXT>This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EXTRF</NAME>
<DESCRIPTION>External Reset Flag</DESCRIPTION>
<TEXT>This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORF</NAME>
<DESCRIPTION>Power-on reset flag</DESCRIPTION>
<TEXT>This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUSR>
<OSCCAL>
<NAME>OSCCAL</NAME>
<DESCRIPTION>Oscillator Calibration Value</DESCRIPTION>
<TEXT>Writing the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table 14</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$66</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT6>
<NAME>CAL6</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit6</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>CAL5</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit5</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>CAL4</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit4</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CAL3</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit3</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CAL2</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit2</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CAL1</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit1</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CAL0</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit0</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OSCCAL>
<CLKPR>
<NAME>CLKPR</NAME>
<DESCRIPTION/>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$61</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>CLKPCE</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT7>
<BIT3>
<NAME>CLKPS3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT3>
<BIT2>
<NAME>CLKPS2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT2>
<BIT1>
<NAME>CLKPS1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT1>
<BIT0>
<NAME>CLKPS0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT0>
</CLKPR>
<SMCR>
<NAME>SMCR</NAME>
<DESCRIPTION>Sleep Mode Control Register</DESCRIPTION>
<TEXT>The Sleep Mode Control Register contains control bits for power management.</TEXT>
<IO_ADDR>$33</IO_ADDR>
<MEM_ADDR>$53</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>SM2</NAME>
<DESCRIPTION>Sleep Mode Select bit 2</DESCRIPTION>
<TEXT>These bits select between the five available sleep modes.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SM1</NAME>
<DESCRIPTION>Sleep Mode Select bit 1</DESCRIPTION>
<TEXT>These bits select between the five available sleep modes.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SM0</NAME>
<DESCRIPTION>Sleep Mode Select bit 0</DESCRIPTION>
<TEXT>These bits select between the five available sleep modes.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SE</NAME>
<DESCRIPTION>Sleep Enable</DESCRIPTION>
<TEXT>The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SMCR>
<GPIOR3>
<NAME>GPIOR3</NAME>
<DESCRIPTION>General Purpose IO Register 3</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1B</IO_ADDR>
<MEM_ADDR>$3B</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>GPIOR37</NAME>
<DESCRIPTION>General Purpose IO Register 3 bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>GPIOR36</NAME>
<DESCRIPTION>General Purpose IO Register 3 bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>GPIOR35</NAME>
<DESCRIPTION>General Purpose IO Register 3 bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>GPIOR34</NAME>
<DESCRIPTION>General Purpose IO Register 3 bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>GPIOR33</NAME>
<DESCRIPTION>General Purpose IO Register 3 bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>GPIOR32</NAME>
<DESCRIPTION>General Purpose IO Register 3 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>GPIOR31</NAME>
<DESCRIPTION>General Purpose IO Register 3 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>GPIOR30</NAME>
<DESCRIPTION>General Purpose IO Register 3 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GPIOR3>
<GPIOR2>
<NAME>GPIOR2</NAME>
<DESCRIPTION>General Purpose IO Register 2</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1A</IO_ADDR>
<MEM_ADDR>$3A</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>GPIOR27</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>GPIOR26</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>GPIOR25</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>GPIOR24</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>GPIOR23</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>GPIOR22</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>GPIOR21</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>GPIOR20</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GPIOR2>
<GPIOR1>
<NAME>GPIOR1</NAME>
<DESCRIPTION>General Purpose IO Register 1</DESCRIPTION>
<TEXT/>
<IO_ADDR>$19</IO_ADDR>
<MEM_ADDR>$39</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>GPIOR17</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>GPIOR16</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>GPIOR15</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>GPIOR14</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>GPIOR13</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>GPIOR12</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>GPIOR11</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>GPIOR10</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GPIOR1>
<GPIOR0>
<NAME>GPIOR0</NAME>
<DESCRIPTION>General Purpose IO Register 0</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1E</IO_ADDR>
<MEM_ADDR>$3E</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>GPIOR07</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>GPIOR06</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>GPIOR05</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>GPIOR04</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>GPIOR03</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>GPIOR02</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>GPIOR01</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>GPIOR00</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GPIOR0>
<PLLCSR>
<NAME>PLLCSR</NAME>
<DESCRIPTION>PLL Control And Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$29</IO_ADDR>
<MEM_ADDR>$49</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT2>
<NAME>PLLF</NAME>
<DESCRIPTION>PLL Factor</DESCRIPTION>
<TEXT>The PLLF bit is used to select the division factor of the PLL.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PLLE</NAME>
<DESCRIPTION>PLL Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PLOCK</NAME>
<DESCRIPTION>PLL Lock Detector</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PLLCSR>
</CPU>
<PORTE>
<LIST>[PORTE:DDRE:PINE]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTE>
<NAME>PORTE</NAME>
<DESCRIPTION>Port E Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0E</IO_ADDR>
<MEM_ADDR>$2E</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT2>
<NAME>PORTE2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTE1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTE0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTE>
<DDRE>
<NAME>DDRE</NAME>
<DESCRIPTION>Port E Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0D</IO_ADDR>
<MEM_ADDR>$2D</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT2>
<NAME>DDE2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDE1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDE0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRE>
<PINE>
<NAME>PINE</NAME>
<DESCRIPTION>Port E Input Pins</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0C</IO_ADDR>
<MEM_ADDR>$2C</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT2>
<NAME>PINE2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINE1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINE0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINE>
</PORTE>
<TIMER_COUNTER_0>
<LIST>[TIMSK0:TIFR0:TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:GTCCR]</LIST>
<LINK/>
<ICON>io_timer.bmp</ICON>
<ID>At8pwm0_12</ID>
<TEXT/>
<TIMSK0>
<NAME>TIMSK0</NAME>
<DESCRIPTION>Timer/Counter0 Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6E</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT2>
<NAME>OCIE0B</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Match B Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCIE0A</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Match A Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOIE0</NAME>
<DESCRIPTION>Timer/Counter0 Overflow Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIMSK0>
<TIFR0>
<NAME>TIFR0</NAME>
<DESCRIPTION>Timer/Counter0 Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$15</IO_ADDR>
<MEM_ADDR>$35</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT2>
<NAME>OCF0B</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Flag 0B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCF0A</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Flag 0A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOV0</NAME>
<DESCRIPTION>Timer/Counter0 Overflow Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIFR0>
<TCCR0A>
<NAME>TCCR0A</NAME>
<DESCRIPTION>Timer/Counter Control Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>$24</IO_ADDR>
<MEM_ADDR>$44</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>COM0A1</NAME>
<DESCRIPTION>Compare Output Mode, Phase Correct PWM Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>COM0A0</NAME>
<DESCRIPTION>Compare Output Mode, Phase Correct PWM Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM0B1</NAME>
<DESCRIPTION>Compare Output Mode, Fast PWm</DESCRIPTION>
<TEXT/>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM0B0</NAME>
<DESCRIPTION>Compare Output Mode, Fast PWm</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT1>
<NAME>WGM01</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WGM00</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR0A>
<TCCR0B>
<NAME>TCCR0B</NAME>
<DESCRIPTION>Timer/Counter Control Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$25</IO_ADDR>
<MEM_ADDR>$45</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>FOC0A</NAME>
<DESCRIPTION>Force Output Compare A</DESCRIPTION>
<TEXT/>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>FOC0B</NAME>
<DESCRIPTION>Force Output Compare B</DESCRIPTION>
<TEXT/>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT3>
<NAME>WGM02</NAME>
<DESCRIPTION/>
<TEXT/>
<ACESS>RW</ACESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS02</NAME>
<DESCRIPTION>Clock Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS01</NAME>
<DESCRIPTION>Clock Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS00</NAME>
<DESCRIPTION>Clock Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR0B>
<TCNT0>
<NAME>TCNT0</NAME>
<DESCRIPTION>Timer/Counter0</DESCRIPTION>
<TEXT>The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register.</TEXT>
<IO_ADDR>$26</IO_ADDR>
<MEM_ADDR>$46</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT0_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT0_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT0_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT0_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT0_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT0_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT0_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT0_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT0>
<OCR0A>
<NAME>OCR0A</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Register</DESCRIPTION>
<TEXT>The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.</TEXT>
<IO_ADDR>$27</IO_ADDR>
<MEM_ADDR>$47</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR0_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR0_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR0_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR0_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR0_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0A>
<OCR0B>
<NAME>OCR0B</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Register</DESCRIPTION>
<TEXT>The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.</TEXT>
<IO_ADDR>$28</IO_ADDR>
<MEM_ADDR>$48</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR0_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR0_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR0_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR0_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR0_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0B>
<GTCCR>
<NAME>GTCCR</NAME>
<DESCRIPTION>General Timer/Counter Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$23</IO_ADDR>
<MEM_ADDR>$43</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TSM</NAME>
<DESCRIPTION>Timer/Counter Synchronization Mode</DESCRIPTION>
<TEXT>Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousl</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICPSEL1</NAME>
<DESCRIPTION>Timer1 Input Capture Selection Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT0>
<NAME>PSR10</NAME>
<DESCRIPTION>Prescaler Reset Timer/Counter1 and Timer/Counter0</DESCRIPTION>
<TEXT>When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GTCCR>
</TIMER_COUNTER_0>
<TIMER_COUNTER_1>
<LIST>[TIMSK1:TIFR1:TCCR1A:TCCR1B:TCCR1C:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L:GTCCR]</LIST>
<LINK>[TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L]</LINK>
<ICON>io_timer.bmp</ICON>
<ID>t16pwm1_12.xml</ID>
<TEXT/>
<TIMSK1>
<NAME>TIMSK1</NAME>
<DESCRIPTION>Timer/Counter Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6F</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>ICIE1</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Interrupt Enable</DESCRIPTION>
<TEXT>When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT2>
<NAME>OCIE1B</NAME>
<DESCRIPTION>Timer/Counter1 Output CompareB Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCIE1A</NAME>
<DESCRIPTION>Timer/Counter1 Output CompareA Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOIE1</NAME>
<DESCRIPTION>Timer/Counter1 Overflow Interrupt Enable</DESCRIPTION>
<TEXT>When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIMSK1>
<TIFR1>
<NAME>TIFR1</NAME>
<DESCRIPTION>Timer/Counter Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$16</IO_ADDR>
<MEM_ADDR>$36</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>ICF1</NAME>
<DESCRIPTION>Input Capture Flag 1</DESCRIPTION>
<TEXT>The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT2>
<NAME>OCF1B</NAME>
<DESCRIPTION>Output Compare Flag 1B</DESCRIPTION>
<TEXT>The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCF1A</NAME>
<DESCRIPTION>Output Compare Flag 1A</DESCRIPTION>
<TEXT>The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOV1</NAME>
<DESCRIPTION>Timer/Counter1 Overflow Flag</DESCRIPTION>
<TEXT>The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIFR1>
<TCCR1A>
<NAME>TCCR1A</NAME>
<DESCRIPTION>Timer/Counter1 Control Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$80</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>COM1A1</NAME>
<DESCRIPTION>Compare Output Mode 1A, bit 1</DESCRIPTION>
<TEXT>The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>COM1A0</NAME>
<DESCRIPTION>Comparet Ouput Mode 1A, bit 0</DESCRIPTION>
<TEXT>The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM1B1</NAME>
<DESCRIPTION>Compare Output Mode 1B, bit 1</DESCRIPTION>
<TEXT>The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM1B0</NAME>
<DESCRIPTION>Compare Output Mode 1B, bit 0</DESCRIPTION>
<TEXT>The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT1>
<NAME>WGM11</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WGM10</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR1A>
<TCCR1B>
<NAME>TCCR1B</NAME>
<DESCRIPTION>Timer/Counter1 Control Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$81</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ICNC1</NAME>
<DESCRIPTION>Input Capture 1 Noise Canceler</DESCRIPTION>
<TEXT>When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICES1</NAME>
<DESCRIPTION>Input Capture 1 Edge Select</DESCRIPTION>
<TEXT>While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT4>
<NAME>WGM13</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WGM12</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS12</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 1</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS11</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 1</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS10</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 1</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR1B>
<TCCR1C>
<NAME>TCCR1C</NAME>
<DESCRIPTION>Timer/Counter1 Control Register C</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$82</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>FOC1A</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>FOC1B</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
</TCCR1C>
<TCNT1H>
<NAME>TCNT1H</NAME>
<DESCRIPTION>Timer/Counter1 High Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rou</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$85</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT1H7</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT1H6</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT1H5</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT1H4</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT1H3</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT1H2</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT1H1</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT1H0</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT1H>
<TCNT1L>
<NAME>TCNT1L</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$84</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT1L7</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT1L6</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT1L5</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT1L4</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT1L3</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT1L2</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT1L1</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT1L0</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT1L>
<OCR1AH>
<NAME>OCR1AH</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$89</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1AH7</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1AH6</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1AH5</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1AH4</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1AH3</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1AH2</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1AH1</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1AH0</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1AH>
<OCR1AL>
<NAME>OCR1AL</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$88</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1AL7</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1AL6</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1AL5</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1AL4</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1AL3</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1AL2</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1AL1</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1AL0</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1AL>
<OCR1BH>
<NAME>OCR1BH</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt ro</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$8B</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1BH7</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1BH6</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1BH5</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1BH4</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1BH3</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1BH2</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1BH1</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1BH0</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1BH>
<OCR1BL>
<NAME>OCR1BL</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rout</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$8A</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1BL7</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1BL6</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1BL5</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1BL4</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1BL3</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1BL2</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1BL1</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1BL0</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1BL>
<ICR1H>
<NAME>ICR1H</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$87</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR1H7</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR1H6</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR1H5</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR1H4</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR1H3</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR1H2</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR1H1</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR1H0</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR1H>
<ICR1L>
<NAME>ICR1L</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inter</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$86</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR1L7</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR1L6</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR1L5</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR1L4</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR1L3</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR1L2</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR1L1</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR1L0</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR1L>
<GTCCR>
<NAME>GTCCR</NAME>
<DESCRIPTION>General Timer/Counter Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$23</IO_ADDR>
<MEM_ADDR>$43</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TSM</NAME>
<DESCRIPTION>Timer/Counter Synchronization Mode</DESCRIPTION>
<TEXT>Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneous</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT0>
<NAME>PSRSYNC</NAME>
<DESCRIPTION>Prescaler Reset Timer/Counter1 and Timer/Counter0</DESCRIPTION>
<TEXT>When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GTCCR>
</TIMER_COUNTER_1>
<AD_CONVERTER>
<LIST>[ADMUX:ADCSRA:ADCH:ADCL:ADCSRB:DIDR0:DIDR1]</LIST>
<LINK/>
<RULES>((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]);</RULES>
<ICON>io_analo.bmp</ICON>
<ID/>
<TEXT>AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noi</TEXT>
<ADMUX>
<NAME>ADMUX</NAME>
<DESCRIPTION>The ADC multiplexer Selection Register</DESCRIPTION>
<TEXT>These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7C</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>REFS1</NAME>
<DESCRIPTION>Reference Selection Bit 1</DESCRIPTION>
<TEXT>These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>REFS0</NAME>
<DESCRIPTION>Reference Selection Bit 0</DESCRIPTION>
<TEXT>These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADLAR</NAME>
<DESCRIPTION>Left Adjust Result</DESCRIPTION>
<TEXT>The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT3>
<NAME>MUX3</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>MUX2</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>MUX1</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>MUX0</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADMUX>
<ADCSRA>
<NAME>ADCSRA</NAME>
<DESCRIPTION>The ADC Control and Status register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ADEN</NAME>
<DESCRIPTION>ADC Enable</DESCRIPTION>
<TEXT>Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADSC</NAME>
<DESCRIPTION>ADC Start Conversion</DESCRIPTION>
<TEXT>In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADATE</NAME>
<DESCRIPTION>ADC Auto Trigger Enable</DESCRIPTION>
<TEXT>When this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADIF</NAME>
<DESCRIPTION>ADC Interrupt Flag</DESCRIPTION>
<TEXT>This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADIE</NAME>
<DESCRIPTION>ADC Interrupt Enable</DESCRIPTION>
<TEXT>When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADPS2</NAME>
<DESCRIPTION>ADC Prescaler Select Bits</DESCRIPTION>
<TEXT>These bits determine the division factor between the XTAL frequency and the input clock to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADPS1</NAME>
<DESCRIPTION>ADC Prescaler Select Bits</DESCRIPTION>
<TEXT>These bits determine the division factor between the XTAL frequency and the input clock to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADPS0</NAME>
<DESCRIPTION>ADC Prescaler Select Bits</DESCRIPTION>
<TEXT>These bits determine the division factor between the XTAL frequency and the input clock to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCSRA>
<ADCH>
<NAME>ADCH</NAME>
<DESCRIPTION>ADC Data Register High Byte</DESCRIPTION>
<TEXT>When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adj</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$79</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ADCH7</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADCH6</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADCH5</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADCH4</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADCH3</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADCH2</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADCH1</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADCH0</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCH>
<ADCL>
<NAME>ADCL</NAME>
<DESCRIPTION>ADC Data Register Low Byte</DESCRIPTION>
<TEXT>When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right a</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$78</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ADCL7</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADCL6</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADCL5</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADCL4</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADCL3</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADCL2</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADCL1</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADCL0</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCL>
<ADCSRB>
<NAME>ADCSRB</NAME>
<DESCRIPTION>ADC Control and Status Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7B</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ADHSM</NAME>
<DESCRIPTION>ADC High Speed Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT4>
<NAME>ADASCR</NAME>
<DESCRIPTION>ADC on Amplified Channel Start Conversion Request Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADTS3</NAME>
<DESCRIPTION>ADC Auto Trigger Source 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADTS2</NAME>
<DESCRIPTION>ADC Auto Trigger Source 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADTS1</NAME>
<DESCRIPTION>ADC Auto Trigger Source 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADTS0</NAME>
<DESCRIPTION>ADC Auto Trigger Source 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCSRB>
<DIDR0>
<NAME>DIDR0</NAME>
<DESCRIPTION>Digital Input Disable Register 0</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7E</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ADC7D</NAME>
<DESCRIPTION>ADC7 Digital input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS/>
<INIT_VAL/>
</BIT7>
<BIT6>
<NAME>ADC6D</NAME>
<DESCRIPTION>ADC6 Digital input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS/>
<INIT_VAL/>
</BIT6>
<BIT5>
<NAME>ADC5D</NAME>
<DESCRIPTION>ADC5 Digital input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS/>
<INIT_VAL/>
</BIT5>
<BIT4>
<NAME>ADC4D</NAME>
<DESCRIPTION>ADC4 Digital input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS/>
<INIT_VAL/>
</BIT4>
<BIT3>
<NAME>ADC3D</NAME>
<DESCRIPTION>ADC3 Digital input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS/>
<INIT_VAL/>
</BIT3>
<BIT2>
<NAME>ADC2D</NAME>
<DESCRIPTION>ADC2 Digital input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS/>
<INIT_VAL/>
</BIT2>
<BIT1>
<NAME>ADC1D</NAME>
<DESCRIPTION>ADC1 Digital input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS/>
<INIT_VAL/>
</BIT1>
<BIT0>
<NAME>ADC0D</NAME>
<DESCRIPTION>ADC0 Digital input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS/>
<INIT_VAL/>
</BIT0>
</DIDR0>
<DIDR1>
<NAME/>
<DESCRIPTION/>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7F</MEM_ADDR>
<ICON/>
<DISPLAY_BITS/>
<BIT5>
<NAME>ACMP0D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT5>
<BIT4>
<NAME>AMP0PD</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT4>
<BIT3>
<NAME>AMP0ND</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT3>
<BIT2>
<NAME>ADC10D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT2>
<BIT1>
<NAME>ADC9D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT1>
<BIT0>
<NAME>ADC8D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT0>
</DIDR1>
</AD_CONVERTER>
<USART>
<LIST>[UDR:UCSRA:UCSRB:UCSRC:UBRRH:UBRRL]</LIST>
<LINK/>
<ICON>io_com.bmp</ICON>
<ID>Usart_00</ID>
<TEXT/>
<UDR>
<NAME>UDR</NAME>
<DESCRIPTION>USART I/O Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC6</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UDR7</NAME>
<DESCRIPTION>USART I/O Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UDR6</NAME>
<DESCRIPTION>USART I/O Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDR5</NAME>
<DESCRIPTION>USART I/O Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UDR4</NAME>
<DESCRIPTION>USART I/O Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UDR3</NAME>
<DESCRIPTION>USART I/O Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UDR2</NAME>
<DESCRIPTION>USART I/O Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UDR1</NAME>
<DESCRIPTION>USART I/O Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UDR0</NAME>
<DESCRIPTION>USART I/O Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UDR>
<UCSRA>
<NAME>UCSRA</NAME>
<DESCRIPTION>USART Control and Status register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC0</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXC</NAME>
<DESCRIPTION>USART Receive Complete</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXC</NAME>
<DESCRIPTION>USART Transmitt Complete</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRE</NAME>
<DESCRIPTION>USART Data Register Empty</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>FE</NAME>
<DESCRIPTION>Framing Error</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DOR</NAME>
<DESCRIPTION>Data Overrun</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UPE</NAME>
<DESCRIPTION>USART Parity Error</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>U2X</NAME>
<DESCRIPTION>Double USART Transmission Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>MPCM</NAME>
<DESCRIPTION>Multi-processor Communication Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSRA>
<UCSRB>
<NAME>UCSRB</NAME>
<DESCRIPTION>USART Control an Status register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC1</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXCIE</NAME>
<DESCRIPTION>RX Complete Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXCIE</NAME>
<DESCRIPTION>TX Complete Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRIE</NAME>
<DESCRIPTION>USART Data Register Empty Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>RXEN</NAME>
<DESCRIPTION>Receiver Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TXEN</NAME>
<DESCRIPTION>Transmitter Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UCSZ2</NAME>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>RXB8</NAME>
<DESCRIPTION>Receive Data Bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TXB8</NAME>
<DESCRIPTION>Transmit Data Bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSRB>
<UCSRC>
<NAME>UCSRC</NAME>
<DESCRIPTION>USART Control an Status register C</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC2</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT6>
<NAME>UMSEL0</NAME>
<DESCRIPTION>USART Mode Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UPM1</NAME>
<DESCRIPTION>Parity Mode Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UPM0</NAME>
<DESCRIPTION>Parity Mode Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>USBS</NAME>
<DESCRIPTION>Stop Bit Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UCSZ1</NAME>
<DESCRIPTION>Character Size Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UCSZ0</NAME>
<DESCRIPTION>Character Size Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UCPOL</NAME>
<DESCRIPTION>Clock Polarity</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSRC>
<UBRRH>
<NAME>UBRRH</NAME>
<DESCRIPTION>USART Baud Rate Register High Byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC5</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>UBRR11</NAME>
<DESCRIPTION>USART Baud Rate Register Bit 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR10</NAME>
<DESCRIPTION>USART Baud Rate Register Bit 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR9</NAME>
<DESCRIPTION>USART Baud Rate Register Bit 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR8</NAME>
<DESCRIPTION>USART Baud Rate Register Bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRRH>
<UBRRL>
<NAME>UBRRL</NAME>
<DESCRIPTION>USART Baud Rate Register Low Byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC4</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>UBRR7</NAME>
<DESCRIPTION>USART Baud Rate Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UBRR6</NAME>
<DESCRIPTION>USART Baud Rate Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UBRR5</NAME>
<DESCRIPTION>USART Baud Rate Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UBRR4</NAME>
<DESCRIPTION>USART Baud Rate Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UBRR3</NAME>
<DESCRIPTION>USART Baud Rate Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR2</NAME>
<DESCRIPTION>USART Baud Rate Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR1</NAME>
<DESCRIPTION>USART Baud Rate Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR0</NAME>
<DESCRIPTION>USART Baud Rate Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRRL>
</USART>
<SPI>
<LIST>[SPDR:SPSR:SPCR]</LIST>
<LINK/>
<ICON>io_com.bmp</ICON>
<ID/>
<TEXT>The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Four Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wakeup from Idle Mode (Slave Mode Only)</TEXT>
<SPCR>
<NAME>SPCR</NAME>
<DESCRIPTION>SPI Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$2C</IO_ADDR>
<MEM_ADDR>$4C</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SPIE</NAME>
<DESCRIPTION>SPI Interrupt Enable</DESCRIPTION>
<TEXT>This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SPE</NAME>
<DESCRIPTION>SPI Enable</DESCRIPTION>
<TEXT>When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DORD</NAME>
<DESCRIPTION>Data Order</DESCRIPTION>
<TEXT>When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>MSTR</NAME>
<DESCRIPTION>Master/Slave Select</DESCRIPTION>
<TEXT>This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CPOL</NAME>
<DESCRIPTION>Clock polarity</DESCRIPTION>
<TEXT>When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CPHA</NAME>
<DESCRIPTION>Clock Phase</DESCRIPTION>
<TEXT>Refer to Figure 36 or Figure 37 for the functionality of this bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SPR1</NAME>
<DESCRIPTION>SPI Clock Rate Select 1</DESCRIPTION>
<TEXT>These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPR0</NAME>
<DESCRIPTION>SPI Clock Rate Select 0</DESCRIPTION>
<TEXT>These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPCR>
<SPSR>
<NAME>SPSR</NAME>
<DESCRIPTION>SPI Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$2D</IO_ADDR>
<MEM_ADDR>$4D</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SPIF</NAME>
<DESCRIPTION>SPI Interrupt Flag</DESCRIPTION>
<TEXT>When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>WCOL</NAME>
<DESCRIPTION>Write Collision Flag</DESCRIPTION>
<TEXT>The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT0>
<NAME>SPI2X</NAME>
<DESCRIPTION>Double SPI Speed Bit</DESCRIPTION>
<TEXT>When this bit is written logic one the SPI speed (SCK Frequency)will be doubled when the SPI is in master mode .This means that the minimum SCK period will be 2 CPU clock periods.When the SPI is configured as Slave,the SPI is only guaranteed to work at f osc /4orlower. The SPI interface on the ATmega162 is also used for program memory and EEPROM downloading or uploading. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPSR>
<SPDR>
<NAME>SPDR</NAME>
<DESCRIPTION>SPI Data Register</DESCRIPTION>
<TEXT>The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.</TEXT>
<IO_ADDR>$2E</IO_ADDR>
<MEM_ADDR>$4E</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SPDR7</NAME>
<DESCRIPTION>SPI Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SPDR6</NAME>
<DESCRIPTION>SPI Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SPDR5</NAME>
<DESCRIPTION>SPI Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SPDR4</NAME>
<DESCRIPTION>SPI Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SPDR3</NAME>
<DESCRIPTION>SPI Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SPDR2</NAME>
<DESCRIPTION>SPI Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SPDR1</NAME>
<DESCRIPTION>SPI Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPDR0</NAME>
<DESCRIPTION>SPI Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPDR>
</SPI>
<WATCHDOG>
<LIST>[WDTCSR]</LIST>
<LINK/>
<ICON>io_watch.bmp</ICON>
<ID/>
<TEXT/>
<WDTCSR>
<NAME>WDTCSR</NAME>
<DESCRIPTION>Watchdog Timer Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$60</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>WDIF</NAME>
<DESCRIPTION>Watchdog Timeout Interrupt Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>WDIE</NAME>
<DESCRIPTION>Watchdog Timeout Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>WDP3</NAME>
<DESCRIPTION>Watchdog Timer Prescaler Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>WDCE</NAME>
<DESCRIPTION>Watchdog Change Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WDE</NAME>
<DESCRIPTION>Watch Dog Enable</DESCRIPTION>
<TEXT>When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>WDP2</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>WDP1</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WDP0</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</WDTCSR>
</WATCHDOG>
<EXTERNAL_INTERRUPT>
<LIST>[EICRA:EIMSK:EIFR]</LIST>
<LINK/>
<ICON>io_ext.bmp</ICON>
<ID/>
<TEXT>The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt</TEXT>
<EICRA>
<NAME>EICRA</NAME>
<DESCRIPTION>External Interrupt Control Register A</DESCRIPTION>
<TEXT>This Register can not be reached in ATmega103 compatibility mode, but the initial value defines INT3:0 as low level inter-rupts,as in ATmega103. • Bits 7..0 - ISC31, ISC30 - ISC00, ISC00: External Interrupt 3-0 Sense Control bits The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 47. Edges on INT3..INT0 are registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 48 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR register before the interrupt is re-enable</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$69</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>ISC21</NAME>
<DESCRIPTION>External Interrupt Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ISC20</NAME>
<DESCRIPTION>External Interrupt Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ISC11</NAME>
<DESCRIPTION>External Interrupt Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ISC10</NAME>
<DESCRIPTION>External Interrupt Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ISC01</NAME>
<DESCRIPTION>External Interrupt Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ISC00</NAME>
<DESCRIPTION>External Interrupt Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EICRA>
<EIMSK>
<NAME>EIMSK</NAME>
<DESCRIPTION>External Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1D</IO_ADDR>
<MEM_ADDR>$3D</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT2>
<NAME>INT2</NAME>
<DESCRIPTION>External Interrupt Request 2 Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>INT1</NAME>
<DESCRIPTION>External Interrupt Request 1 Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>INT0</NAME>
<DESCRIPTION>External Interrupt Request 0 Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EIMSK>
<EIFR>
<NAME>EIFR</NAME>
<DESCRIPTION>External Interrupt Flag Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1C</IO_ADDR>
<MEM_ADDR>$3C</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT2>
<NAME>INTF2</NAME>
<DESCRIPTION>External Interrupt Flag 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>INTF1</NAME>
<DESCRIPTION>External Interrupt Flag 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>INTF0</NAME>
<DESCRIPTION>External Interrupt Flag 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EIFR>
</EXTERNAL_INTERRUPT>
<EEPROM>
<LIST>[EEARH:EEARL:EEDR:EECR]</LIST>
<LINK>[EEARH:EEARL]</LINK>
<ICON>io_cpu.bmp</ICON>
<ID/>
<TEXT>EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute</TEXT>
<EEARH>
<NAME>EEARH</NAME>
<DESCRIPTION>EEPROM Read/Write Access High Byte</DESCRIPTION>
<TEXT>Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. </TEXT>
<IO_ADDR>$22</IO_ADDR>
<MEM_ADDR>$42</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>EEAR11</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEAR10</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEAR9</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEAR8</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEARH>
<EEARL>
<NAME>EEARL</NAME>
<DESCRIPTION>EEPROM Read/Write Access Low Byte</DESCRIPTION>
<TEXT>Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. </TEXT>
<IO_ADDR>$21</IO_ADDR>
<MEM_ADDR>$41</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>EEARL7</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>EEARL6</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>EEARL5</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEARL4</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EEARL3</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEARL2</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEARL1</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEARL0</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEARL>
<EEDR>
<NAME>EEDR</NAME>
<DESCRIPTION>EEPROM Data Register</DESCRIPTION>
<TEXT>For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.</TEXT>
<IO_ADDR>$20</IO_ADDR>
<MEM_ADDR>$40</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>EEDR7</NAME>
<DESCRIPTION>EEPROM Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>EEDR6</NAME>
<DESCRIPTION>EEPROM Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>EEDR5</NAME>
<DESCRIPTION>EEPROM Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEDR4</NAME>
<DESCRIPTION>EEPROM Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EEDR3</NAME>
<DESCRIPTION>EEPROM Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEDR2</NAME>
<DESCRIPTION>EEPROM Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEDR1</NAME>
<DESCRIPTION>EEPROM Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEDR0</NAME>
<DESCRIPTION>EEPROM Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEDR>
<EECR>
<NAME>EECR</NAME>
<DESCRIPTION>EEPROM Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1F</IO_ADDR>
<MEM_ADDR>$3F</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>EEPM1</NAME>
<DESCRIPTION>EEPROM Programming Mode Bit 1</DESCRIPTION>
<TEXT>The EEPROM Programming mode bit setting defines which programming action will be triggered when writing EEWE.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEPM0</NAME>
<DESCRIPTION>EEPROM Programming Mode Bit 0</DESCRIPTION>
<TEXT>The EEPROM Programming mode bit setting defines which programming action will be triggered when writing EEWE.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EERIE</NAME>
<DESCRIPTION>EEPROM Ready Interrupt Enable</DESCRIPTION>
<TEXT>EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEMWE</NAME>
<DESCRIPTION>EEPROM Master Write Enable</DESCRIPTION>
<TEXT>The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEWE</NAME>
<DESCRIPTION>EEPROM Write Enable</DESCRIPTION>
<TEXT>The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EERE</NAME>
<DESCRIPTION>EEPROM Read Enable</DESCRIPTION>
<TEXT>The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EECR>
</EEPROM>
</IO_MODULE><ICE_SETTINGS><MODULE_LIST>[JTAGICEmkII:STK500_2:STK500:SIMULATOR:AVRISPmkII]</MODULE_LIST><JTAGICEmkII>
<ID>0x9381</ID>
<Interface>DebugWire</Interface>
<!--Bit 0 in byte 0 is I/O location 0, bit 7 in byte 7 is I/O location 63-->
<ucRead>0xF8,0x7F,0x60,0xFE,0xFF,0x33,0xBD,0xE0</ucRead>
<ucWrite>0xF8,0x7F,0x40,0xEE,0xFF,0x33,0xBC,0xE0</ucWrite>
<ucReadShadow>0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00</ucReadShadow>
<ucWriteShadow>0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00</ucWriteShadow>
<!--Bit 0 in byte 0 is extended I/O location 96, bit 7 in byte 19 is I/O location 255-->
<ucExtRead>0x53,0xC2,0xC0,0xDF,0xF7,0x0F,0x00,0x00,0x3F,0xE4,0x00,0x00,0x36,0x37,0x01,0xFC,0x05,0xFC,0x07,0xFC</ucExtRead>
<ucExtWrite>0x11,0xC2,0xC0,0xD8,0xF7,0x0F,0x00,0x00,0x3F,0xE4,0x00,0x00,0x36,0x33,0x01,0xFC,0x05,0xFC,0x07,0xFC</ucExtWrite>
<ucExtReadShadow>0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00</ucExtReadShadow>
<ucExtWriteShadow>0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00</ucExtWriteShadow>
<!--Register locations etc.-->
<ucIDRAddress>0x00</ucIDRAddress>
<ucSPMCAddress>0X00</ucSPMCAddress>
<ucRAMPZAddress>0X00</ucRAMPZAddress>
<ulFlashPageSize>64</ulFlashPageSize>
<ulEepromPageSize>4</ulEepromPageSize>
<ulBootAddress>0x0F80</ulBootAddress>
<BootAddress11>0x0F80</BootAddress11>
<BootAddress10>0x0F00</BootAddress10>
<BootAddress01>0x0E00</BootAddress01>
<BootAddress00>0x0C00</BootAddress00>
<ucUpperExtIOLoc>0xFF</ucUpperExtIOLoc>
<ulFlashSize>0x2000</ulFlashSize>
<ulRegStart>0x0000,32</ulRegStart>
<ulIoStart>0x0020,64</ulIoStart>
<!--Other stuff-->
<DWENmaskExt>0x00</DWENmaskExt>
<DWENmaskHigh>0x40</DWENmaskHigh>
<DWENmaskLow>0x00</DWENmaskLow>
<SPIENmaskExt>0x00</SPIENmaskExt>
<SPIENmaskHigh>0x20</SPIENmaskHigh>
<SPIENmaskLow>0x00</SPIENmaskLow>
<ucEepromInst>0xBD,0xF2,0xBD,0xE1,0xBB,0xCF,0xB4,0x00,0xBE,0x01,0xB6,0x01,0xBC,0x00,0xBB,0xBF,0x99,0xF9,0xBB,0xAF</ucEepromInst>
<ucFlashInst>0xB6,0x01,0x11</ucFlashInst>
<ucSPHaddr>0x3e</ucSPHaddr>
<ucSPLaddr>0x3d</ucSPLaddr>
<DWdatareg>0x31</DWdatareg>
<DWbasePC>0x00</DWbasePC>
<Osccalshared>0x00</Osccalshared>
<ucAllowFullPageBitstream>0x00</ucAllowFullPageBitstream>
<uiStartSmallestBootLoaderSection>0xF80</uiStartSmallestBootLoaderSection>
<ucUseJTAGID>0x00</ucUseJTAGID>
<MSMCRAddress>0x52</MSMCRAddress>
<PSC>0</PSC>
<PSC>2</PSC>
<AC>0</AC>
<AC>1</AC>
<AC>2</AC>
<EECRAddress>0x3f</EECRAddress>
</JTAGICEmkII>
<STK500_2><IspEnterProgMode><timeout>200</timeout><stabDelay>100</stabDelay><cmdexeDelay>25</cmdexeDelay><synchLoops>32</synchLoops><byteDelay>0</byteDelay><pollIndex>3</pollIndex><pollValue>0x53</pollValue></IspEnterProgMode><IspLeaveProgMode><preDelay>1</preDelay><postDelay>1</postDelay></IspLeaveProgMode><IspChipErase><eraseDelay>45</eraseDelay><pollMethod>1</pollMethod></IspChipErase><IspProgramFlash><mode>0x41</mode><blockSize>64</blockSize><delay>10</delay><cmd1>0x40</cmd1><cmd2>0x4C</cmd2><cmd3>0x00</cmd3><pollVal1>0x00</pollVal1><pollVal2>0x00</pollVal2></IspProgramFlash><IspProgramEeprom><mode>0x41</mode><blockSize>4</blockSize><delay>5</delay><cmd1>0xC1</cmd1><cmd2>0xC2</cmd2><cmd3>0x00</cmd3><pollVal1>0x00</pollVal1><pollVal2>0x00</pollVal2></IspProgramEeprom><IspReadFlash><blockSize>256</blockSize></IspReadFlash><IspReadEeprom><blockSize>256</blockSize></IspReadEeprom><IspReadFuse><pollIndex>4</pollIndex></IspReadFuse><IspReadLock><pollIndex>4</pollIndex></IspReadLock><IspReadSign><pollIndex>4</pollIndex></IspReadSign><IspReadOsccal><pollIndex>4</pollIndex></IspReadOsccal><PPControlStack>0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00</PPControlStack><PpEnterProgMode><stabDelay>100</stabDelay><progModeDelay>0</progModeDelay><latchCycles>5</latchCycles><toggleVtg>1</toggleVtg><powerOffDelay>15</powerOffDelay><resetDelayMs>1</resetDelayMs><resetDelayUs>0</resetDelayUs></PpEnterProgMode><PpLeaveProgMode><stabDelay>15</stabDelay><resetDelay>15</resetDelay></PpLeaveProgMode><PpChipErase><pulseWidth>0</pulseWidth><pollTimeout>10</pollTimeout></PpChipErase><PpProgramFlash><pollTimeout>5</pollTimeout><mode>0x0D</mode><blockSize>256</blockSize></PpProgramFlash><PpReadFlash><blockSize>256</blockSize></PpReadFlash><PpProgramEeprom><pollTimeout>5</pollTimeout><mode>0x05</mode><blockSize>256</blockSize></PpProgramEeprom><PpReadEeprom><blockSize>256</blockSize></PpReadEeprom><PpProgramFuse><pulseWidth>0</pulseWidth><pollTimeout>5</pollTimeout></PpProgramFuse><PpProgramLock><pulseWidth>0</pulseWidth><pollTimeout>5</pollTimeout></PpProgramLock></STK500_2><STK500>
<DeviceId>0x65</DeviceId>
<SelfTimed>1</SelfTimed>
<FullParallel>1</FullParallel>
<Polled>1</Polled>
<FPoll>0xFF</FPoll>
<EPol1>0xFF</EPol1>
<EPol2>0xFF</EPol2>
<ComLockFuseRead>0</ComLockFuseRead>
<ResetDisable>1</ResetDisable>
</STK500>
<SIMULATOR>
<CoreID>AVRSimCoreV2.SimCoreV2</CoreID>
<MemoryID>AVRSimMemory8bit.SimMemory8bit</MemoryID>
<InterruptID>AVRSimInterrupt.SimInterrupt</InterruptID>
<EEINTERRUPT>0x1a</EEINTERRUPT>
<EEAR_EXTRA_BIT>0</EEAR_EXTRA_BIT>
<NmbIOModules>14</NmbIOModules>
<PORTB>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTB>
<PORTD>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTD>
<PORTE>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTE>
<EXTINT0>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x0A</IntVector>
<EnableIOAdr>0x1D</EnableIOAdr>
<EnableMask>0x01</EnableMask>
<FlagIOAdr>0x1C</FlagIOAdr>
<FlagMask>0x01</FlagMask>
<ExtPinIOAdr>0x09</ExtPinIOAdr>
<ExtPinMask>0x01</ExtPinMask>
<SenseIOAdr>0x49</SenseIOAdr>
<SenseMask>0x03</SenseMask>
</EXTINT0>
<EXTINT1>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x13</IntVector>
<EnableIOAdr>0x1D</EnableIOAdr>
<EnableMask>0x02</EnableMask>
<FlagIOAdr>0x1C</FlagIOAdr>
<FlagMask>0x02</FlagMask>
<ExtPinIOAdr>0x09</ExtPinIOAdr>
<ExtPinMask>0x02</ExtPinMask>
<SenseIOAdr>0x49</SenseIOAdr>
<SenseMask>0x0c</SenseMask>
</EXTINT1>
<EXTINT2>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x18</IntVector>
<EnableIOAdr>0x1D</EnableIOAdr>
<EnableMask>0x04</EnableMask>
<FlagIOAdr>0x1C</FlagIOAdr>
<FlagMask>0x04</FlagMask>
<ExtPinIOAdr>0x09</ExtPinIOAdr>
<ExtPinMask>0x04</ExtPinMask>
<SenseIOAdr>0x49</SenseIOAdr>
<SenseMask>0x30</SenseMask>
</EXTINT2>
<EXTINT3>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x1C</IntVector>
<EnableIOAdr>0x1D</EnableIOAdr>
<EnableMask>0x08</EnableMask>
<FlagIOAdr>0x1C</FlagIOAdr>
<FlagMask>0x08</FlagMask>
<ExtPinIOAdr>0x09</ExtPinIOAdr>
<ExtPinMask>0x08</ExtPinMask>
<SenseIOAdr>0x49</SenseIOAdr>
<SenseMask>0xc0</SenseMask>
</EXTINT3>
<TIMER0>
<ID>AvrSimIOtim8pwmsync2.tim8pwmsync2</ID>
<OvfVector>0x0011</OvfVector>
<CompAVector>0x0010</CompAVector>
<CompBVector>0x001B</CompBVector>
<OCnAport>PORTD</OCnAport>
<OCnAbit>3</OCnAbit>
<OCnBport>PORTE</OCnBport>
<OCnBbit>1</OCnBbit>
<TxPort>PINC</TxPort>
<TxBit>2</TxBit>
</TIMER0>
<TIMER1>
<ID>AVRSimIOTimert16pwm1.SimIOTimert16pwm1</ID>
<IcpVector>0x0B</IcpVector>
<CompAVector>0x0C</CompAVector>
<CompBVector>0x0D</CompBVector>
<OvfVector>0x0F</OvfVector>
<CountPinAdr>0x09</CountPinAdr>
<CountPinMask>0x40</CountPinMask>
<IcpPinAdr>0x09</IcpPinAdr>
<IcpPinMask>0x10</IcpPinMask>
<OutputAAdr>0x05</OutputAAdr>
<OutputAMask>0x20</OutputAMask>
<OutputBAdr>0x05</OutputBAdr>
<OutputBMask>0x40</OutputBMask>
<OutputCAdr>0x05</OutputCAdr>
<OutputCMask>0x80</OutputCMask>
</TIMER1>
<SPM>
<ID>AVRSimIOSPM.SimIOSPM</ID>
<IntVector>0x1F</IntVector>
</SPM>
<SPI>
<ID>AVRSimIOSpi.SimIOSpi</ID>
<IntVector>0x14</IntVector>
<SCKAddress>0x03</SCKAddress>
<SCKMask>0x02</SCKMask>
<MISOAddress>0x03</MISOAddress>
<MISOMask>0x08</MISOMask>
<MOSIAddress>0x03</MOSIAddress>
<MOSIMask>0x04</MOSIMask>
<SSAddress>0x03</SSAddress>
<DIRAddress>0x04</DIRAddress>
<SSMask>0x01</SSMask>
</SPI>
<USART>
<ID>AVRSimIOUsart.SimIOUsart</ID>
<RXVector>0x15</RXVector>
<TXVector>0x17</TXVector>
<UDREVector>0x16</UDREVector>
<TXPinAddress>0x0C</TXPinAddress>
<TXPinMask>0x02</TXPinMask>
<RXPinAddress>0x0C</RXPinAddress>
<RXPinMask>0x01</RXPinMask>
</USART>
<WATCHDOG>
<ID>AvrMasterTimer.MasterTimer</ID>
<Frequency>128</Frequency>
<Version>1</Version>
<IntVector>0x19</IntVector>
<PrescaleArray>2048:4096:8192:16384:32768:65536:131072:262144:524288:1048576</PrescaleArray>
</WATCHDOG>
<ADC>
<ID>AVRSimADC.SimADC</ID>
<IntVector>0x12</IntVector>
</ADC>
<DEFAULT_SETTINGS>
<HighFuse>0xFF</HighFuse>
<ExtendedFuse>0xff</ExtendedFuse>
<LowFuse>0xFF</LowFuse>
<Lockbit>0xFF</Lockbit>
</DEFAULT_SETTINGS>
</SIMULATOR>
<AVRISPmkII/>
</ICE_SETTINGS></AVRPART>
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